SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
| Offset | Length | Register Name | PDMA1 Physical Address | PDMA0 Physical Address |
|---|---|---|---|---|
| 0h | 32 | ECC_AGGR_REV | 00C0 0000h | 00C0 1000h |
| 8h | 32 | ECC_AGGR_VECTOR | 00C0 0008h | 00C0 1008h |
| Ch | 32 | ECC_AGGR_STAT | 00C0 000Ch | 00C0 100Ch |
| 10h | 32 | ECC_AGGR_RESERVED_SVBUS_J | 00C0 0010h + formula | 00C0 1010h + formula |
| 3Ch | 32 | ECC_AGGR_SEC_EOI_REG | 00C0 003Ch | 00C0 103Ch |
| 40h | 32 | ECC_AGGR_SEC_STATUS_REG0 | 00C0 0040h | 00C0 1040h |
| 80h | 32 | ECC_AGGR_SEC_ENABLE_SET_REG0 | 00C0 0080h | 00C0 1080h |
| C0h | 32 | ECC_AGGR_SEC_ENABLE_CLR_REG0 | 00C0 00C0h | 00C0 10C0h |
| 13Ch | 32 | ECC_AGGR_DED_EOI_REG | 00C0 013Ch | 00C0 113Ch |
| 140h | 32 | ECC_AGGR_DED_STATUS_REG0 | 00C0 0140h | 00C0 1140h |
| 180h | 32 | ECC_AGGR_DED_ENABLE_SET_REG0 | 00C0 0180h | 00C0 1180h |
| 1C0h | 32 | ECC_AGGR_DED_ENABLE_CLR_REG0 | 00C0 01C0h | 00C0 11C0h |
| 200h | 32 | ECC_AGGR_AGGR_ENABLE_SET | 00C0 0200h | 00C0 1200h |
| 204h | 32 | ECC_AGGR_AGGR_ENABLE_CLR | 00C0 0204h | 00C0 1204h |
| 208h | 32 | ECC_AGGR_AGGR_STATUS_SET | 00C0 0208h | 00C0 1208h |
| 20Ch | 32 | ECC_AGGR_AGGR_STATUS_CLR | 00C0 020Ch | 00C0 120Ch |