SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The Asynchronous Audio Sample Rate Converter (ASRC) allows the movement of up to 8 audio stereo streams (16 audio channels) from one audio zone to another audio zone via 8 two-channel sample rate converters.
Each sample rate converter performs a digital audio sample rate conversion between input and output clock zone sample rates. The input and output clock zones can be individually selected for each sample rate converter in stream mode configuration. In group mode configuration, the sample rate converters that make up each group share the same input and output clock zone specifications. Each input and output channel is buffered by a 32-sample FIFO. The FIFO threshold values are programmed to a value between 1 and 16 samples.
The ASRC converts audio data between 4 input and 4 output clock zones. The clock zones provide a sample rate (Fs) input into clock rate estimators on the receive side and transmit side. Each ASRC receive and transmit clock zone input can come from one of 8 possible sources as shown in ASRC Block Diagram. The input clocks and output clocks can have any frequency that is within the constraints specified in ASRC Overview and are completely asynchronous to each other.
The ASRC works by interpolating the input audio signals that are in the sequential domain of the source audio input clock. The input audio signal is interpolated up to 16x the input rate, then resampled at 16x the output rate, and then downsampled to the desired output clock frequency.
ASRC Block Diagram shows a simplified block diagram of ASRC module.
Figure 12-2 ASRC Block DiagramThe ASRC can handle multiple channels and switch between each channel as samples become available. The ASRC external interface is VBUS interface. One VBUS Interface is provided for configuration and status registers and another VBUS interface is dedicated for writing and reading audio samples. The ASRC also generate events when a configurable amount of output samples are ready. The ASRC implemets sample packer modules for processing the different streams as data becomes available.
The ASRC is a loosely coupled coprocessor to the main SoC DSP. Data is moved into the ASRC by device EDMA controller and an event is generated when another block of samples is completed for a given audio stream. In order to minimize the number of EDMA channels and events required, the ASRC also supports group events which are generated only when all of the selected Left and Right channels meet a pre-defined FIFO threshold. This permits a single EDMA transfer to perform the input and a single EDMA transfer to perform the output of all of the channels in the group.
As an alternative to EDMA moderated data input and output ASRC data transfers, the ASRC also supports input FIFO and output FIFO interrupts to permit a device processor to control the data transfers. The ASRC generates an error interrupt when a FIFO overflow and underflow error condition occurs.
The ASRC supports two modes of transferring data into the ASRC data inputs and from the ASRC data outputs: