SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Interrupt Enable Clear Register 0
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| Instance Name | Physical Address |
|---|---|
| DMASS0_ECC_AGGR_0 | 3F00 51C0h |
| 32 | 31 | 30 | 29 | 28 | 27 | 26 | 25 |
| RESERVED | MSRAM_RAMECC0_ENABLE_CLR | SEC_PROXY_BUFRAM_RAMECC_ENABLE_CLR | SEC_PROXY_STRAM_RAMECC_ENABLE_CLR | RINGACC_STRAM_RAMECC_ENABLE_CLR | |||
| NONE | R/W1TC | R/W1TC | R/W1TC | R/W1TC | |||
| 0h | 0h | 0h | 0h | 0h | |||
| 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 |
| MAP_RAMECC_ENABLE_CLR | SR_RAMECC_ENABLE_CLR | BCDMA_RNGOCC_RAMECC_ENABLE_CLR | BCDMA_STS_RAMECC1_ENABLE_CLR | BCDMA_STS_RAMECC0_ENABLE_CLR | BCDMA_RPCF2_RAMECC_ENABLE_CLR | BCDMA_RPCF1_RAMECC_ENABLE_CLR | BCDMA_RPCF0_RAMECC_ENABLE_CLR |
| R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 |
| BCDMA_TPCF1_RAMECC_ENABLE_CLR | BCDMA_TPCF0_RAMECC_ENABLE_CLR | PCFD1_RAMECC_ENABLE_CLR | PCFD0_RAMECC_ENABLE_CLR | BCDMA_STATE_RAMECC_ENABLE_CLR | BCDMA_CFG_RAMECC_ENABLE_CLR | PKTDMA_RNGOCC_RAMECC_ENABLE_CLR | PKTDMA_STS_RAMECC1_ENABLE_CLR |
| R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 |
| PKTDMA_STS_RAMECC0_ENABLE_CLR | PKTDMA_RPCF2_RAMECC_ENABLE_CLR | PKTDMA_RPCF1_RAMECC_ENABLE_CLR | PKTDMA_RPCF0_RAMECC_ENABLE_CLR | PKTDMA_TPCF1_RAMECC_ENABLE_CLR | PKTDMA_TPCF0_RAMECC_ENABLE_CLR | PKTDMA_STATE_RAMECC_ENABLE_CLR | PKTDMA_CFG_RAMECC_ENABLE_CLR |
| R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:28 | RESERVED | NONE | 0h | Reserved |
| 27 | MSRAM_RAMECC0_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for msram_ramecc0_pend |
| 26 | SEC_PROXY_BUFRAM_RAMECC_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for sec_proxy_bufram_ramecc_pend |
| 25 | SEC_PROXY_STRAM_RAMECC_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for sec_proxy_stram_ramecc_pend |
| 24 | RINGACC_STRAM_RAMECC_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for ringacc_stram_ramecc_pend |
| 23 | MAP_RAMECC_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for map_ramecc_pend |
| 22 | SR_RAMECC_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for sr_ramecc_pend |
| 21 | BCDMA_RNGOCC_RAMECC_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for bcdma_rngocc_ramecc_pend |
| 20 | BCDMA_STS_RAMECC1_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for bcdma_sts_ramecc1_pend |
| 19 | BCDMA_STS_RAMECC0_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for bcdma_sts_ramecc0_pend |
| 18 | BCDMA_RPCF2_RAMECC_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for bcdma_rpcf2_ramecc_pend |
| 17 | BCDMA_RPCF1_RAMECC_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for bcdma_rpcf1_ramecc_pend |
| 16 | BCDMA_RPCF0_RAMECC_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for bcdma_rpcf0_ramecc_pend |
| 15 | BCDMA_TPCF1_RAMECC_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for bcdma_tpcf1_ramecc_pend |
| 14 | BCDMA_TPCF0_RAMECC_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for bcdma_tpcf0_ramecc_pend |
| 13 | PCFD1_RAMECC_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for pcfd1_ramecc_pend |
| 12 | PCFD0_RAMECC_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for pcfd0_ramecc_pend |
| 11 | BCDMA_STATE_RAMECC_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for bcdma_state_ramecc_pend |
| 10 | BCDMA_CFG_RAMECC_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for bcdma_cfg_ramecc_pend |
| 9 | PKTDMA_RNGOCC_RAMECC_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for pktdma_rngocc_ramecc_pend |
| 8 | PKTDMA_STS_RAMECC1_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for pktdma_sts_ramecc1_pend |
| 7 | PKTDMA_STS_RAMECC0_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for pktdma_sts_ramecc0_pend |
| 6 | PKTDMA_RPCF2_RAMECC_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for pktdma_rpcf2_ramecc_pend |
| 5 | PKTDMA_RPCF1_RAMECC_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for pktdma_rpcf1_ramecc_pend |
| 4 | PKTDMA_RPCF0_RAMECC_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for pktdma_rpcf0_ramecc_pend |
| 3 | PKTDMA_TPCF1_RAMECC_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for pktdma_tpcf1_ramecc_pend |
| 2 | PKTDMA_TPCF0_RAMECC_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for pktdma_tpcf0_ramecc_pend |
| 1 | PKTDMA_STATE_RAMECC_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for pktdma_state_ramecc_pend |
| 0 | PKTDMA_CFG_RAMECC_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for pktdma_cfg_ramecc_pend |