SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
| Step | Description |
|---|---|
| 1. | Wait 150µs for RAM to power up after reset. The HyperRAM does not provide any feedback on reset/ready state to the HBMC . |
| 2. | Ensure that the FIFO RAM auto-initialization is complete by reading the HYPERBUS_SYSCFG_RAM_STAT_REG[0] INIT_DONE bit . |
| 3. | Lock MDLL: |
| - To ensure that the MDLL in the HyperBus is locked, the reset to the HyperBus module should be de-asserted only after all the clock inputs are stable at the desired operating frequency . The MDLL can lose the lock if the frequencies of the clock inputs to the HyperBus module are changed during operation. | |
| - To ensure that the MDLL is stabilized, the following sequence is required. Boot code should attempt to read 64 bytes of RAM data, for 16 iterations, and if the data is the same in 4 successive iterations, the DLL can be considered to be stabilized and the software proceed with normal RAM access . | |
| - The HYPERBUS_SYSCFG_DLL_STAT_REG [0] MDLL_LOCK and HYPERBUS_SYSCFG_DLL_STAT_REG 1] SDL_LOCK bits can be used to determine if the controller delay line and target delay line have locked, respectively . | |
| 4. | Initialize Memory Configuration register (HYPERBUS_CORE_MCR_J): |
| - HYPERBUS_CORE_MCR_J[31] MAXEN bit and HYPERBUS_CORE_MCR_J[26-18] MAXLEN bit field based on burst transaction length to memory. | |
| - HYPERBUS_CORE_MCR_J[17] TCMO = 0h, since HBMC does not support command merging for HyperRAM accesses. | |
| - HYPERBUS_CORE_MCR_J[16] ACS = 0h, to set 'No asymmetry cache system support'. | |
| - HYPERBUS_CORE_MCR_J[5] CRT = 0h or 1h, depending on what needs to be accessed (memory or register space). | |
| - HYPERBUS_CORE_MCR_J[4] DEVTYPE = 1h, to set 'HyperRAM' instead 'HyperFlash'. | |
| - HYPERBUS_CORE_MCR_J[1-0] WRAPSIZE = 00h, since the HBMC does not support wrap bursts. | |
| 5. | Initialize HYPERBUS_CORE_MTR_J register based on timing of the memory device being used. |
| 6. | Initialize HYPERBUS_CORE_MCR_J register: |
| - HYPERBUS_CORE_MCR_J[31-24] A_MSB = 8 MSB bits of memory address space. This will define the start of the 16 MB address region in the system memory where the HyperRAM can be accesed. The controller will initiate HyperRAM access to any memory mapped access in this range. | |
| 7. | Check the HYPERBUS_SYSCFG_DLL_STAT_REG[0] MDLL_LOCK bit to ensure the Controller DLL is locked. |
| 8. | Normal HyperRAM access can be performed after this. |
| 9. | The HyperRAM device registers can be accessed by read/write transactions to the offset from the base address as specified in the device command summary table with HYPERBUS_CORE_MCR_J[5] CRT bit set to register space. |
| 10. | The HyperRAM memory data array can be read/written to as memory mapped access with HYPERBUS_CORE_MCR_J[5] CRT bit set to memory space. |
HyperRAM devices have a 150µs startup time. Software needs to wait this duration after reset to initiate transactions to a HyperRAM device.