SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Indirect Memory Data Register 1 Data is packed using little endian byte numbering
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| Instance Name | Physical Address |
|---|---|
| C7X256V0_DEBUG | 0007 3400 004Ch |
| C7X256V1_DEBUG | 0007 3800 004Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| DATA1 | |||||||
| R/W | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| DATA1 | |||||||
| R/W | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| DATA1 | |||||||
| R/W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DATA1 | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:0 | DATA1 | R/W | 0h | Data bits of the read or write transaction This bit field holds bits 63:32 of the data of an indirect debug port transaction If Writing data: This register must be written after the address registers If Reading data This register will have valid read data when the transaction is complete [MEM_PORT_STAT == 10b] |