SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The REMote 'n' Address Least Significant word defines the least significant portion of the Remote address for remote cache data storage memory 0. The RL2 cache use up to three remote cache data storage memory ranges to place the L2 data within. The length of these ranges must be greater or equal to the size specified. This register is write protected when ~ienable is set.
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| Instance Name | Physical Address |
|---|---|
| RL2_0 | 2500 0020h + formula |
| RL2_0 | 2500 1020h + formula |
| RL2_2 | 2500 2020h + formula |
| RL2_3 | 2500 3020h + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| ADR_LSW | |||||||
| R/W | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| ADR_LSW | |||||||
| R/W | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| ADR_LSW | RESERVED | ||||||
| R/W | NONE | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:11 | ADR_LSW | R/W | 0h | The ~irem0_adr_lsw defines the LSW of the remote cache data storage memory address[31:11] range 'n' for the RL2 to use for the cache. The remaining bits 10:0 are assumed to be zero. |
| 10:0 | RESERVED | NONE | 0h | Reserved |