SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
PLL Configuration shows the HSDIV values that are programmed by the R5 ROM. This section shows all HSDIV calculations for PLL including items not programmed by ROM. For details on FOUTVCO_P and FOUTPOSTDIV, see PLL Output Clocks.
| PLL POSTDIV | HSDIV | Formula | Notes |
|---|---|---|---|
| 0 | MAIN_PLL0_HSDIV0_CLKOUT | FOUTVCO_P/HSDIV0 | FOUTVCO_P default value is 2000MHz |
| 0 | MAIN_PLL0_HSDIV1_CLKOUT | FOUTVCO_P/HSDIV1 | FOUTVCO_P default value is 2000MHz |
| 0 | MAIN_PLL0_HSDIV2_CLKOUT | FOUTVCO_P/HSDIV2 | FOUTVCO_P default value is 2000MHz |
| 0 | MAIN_PLL0_HSDIV3_CLKOUT | Reserved | Reserved |
| 0 | MAIN_PLL0_HSDIV4_CLKOUT | FOUTVCO_P/HSDIV4 | FOUTVCO_P default value is 2000MHz |
| 1 | MAIN_PLL0_HSDIV5_CLKOUT | FOUTPOSTDIV/HSDIV5 | FOUTPOSTDIV default value is 1000MHz |
| 1 | MAIN_PLL0_HSDIV6_CLKOUT | FOUTPOSTDIV/HSDIV6 | FOUTPOSTDIV default value is 1000MHz |
| 1 | MAIN_PLL0_HSDIV7_CLKOUT | FOUTPOSTDIV/HSDIV7 | FOUTPOSTDIV default value is 1000MHz |
| 1 | MAIN_PLL0_HSDIV8_CLKOUT | FOUTPOSTDIV/HSDIV8 | FOUTPOSTDIV default value is 1000MHz |
| 1 | MAIN_PLL0_HSDIV9_CLKOUT | FOUTPOSTDIV/HSDIV9 | FOUTPOSTDIV default value is 1000MHz |
| PLL POSTDIV | HSDIV | Formula | Notes |
|---|---|---|---|
| 0 | MAIN_PLL1_HSDIV0_CLKOUT | FOUTVCO_P/HSDIV0 | FOUTVCO_P default value is 1920MHz |
| 0 | MAIN_PLL1_HSDIV1_CLKOUT | FOUTVCO_P/HSDIV1 | FOUTVCO_P default value is 1920MHz |
| 0 | MAIN_PLL1_HSDIV2_CLKOUT | FOUTVCO_P/HSDIV2 | FOUTVCO_P default value is 1920MHz |
| 0 | MAIN_PLL1_HSDIV3_CLKOUT | FOUTVCO_P/HSDIV3 | FOUTVCO_P default value is 1920MHz |
| 0 | MAIN_PLL1_HSDIV4_CLKOUT | FOUTVCO_P/HSDIV4 | FOUTVCO_P default value is 1920MHz |
| 1 | MAIN_PLL1_HSDIV5_CLKOUT | FOUTPOSTDIV/HSDIV5 | FOUTPOSTDIV default value is 960MHz |
| 1 | MAIN_PLL1_HSDIV6_CLKOUT | FOUTPOSTDIV/HSDIV6 | FOUTPOSTDIV default value is 960MHz |
| PLL POSTDIV | HSDIV | Formula | Notes |
|---|---|---|---|
| 0 | MAIN_PLL2_HSDIV0_CLKOUT | FOUTVCO_P/HSDIV0 | FOUTVCO_P default value is 2000MHz |
| 0 | MAIN_PLL2_HSDIV1_CLKOUT | FOUTVCO_P/HSDIV1 | FOUTVCO_P default value is 2000MHz |
| 0 | MAIN_PLL2_HSDIV2_CLKOUT | FOUTVCO_P/HSDIV2 | FOUTVCO_P default value is 2000MHz |
| 0 | MAIN_PLL2_HSDIV3_CLKOUT | FOUTVCO_P/HSDIV3 | FOUTVCO_P default value is 2000MHz |
| 0 | MAIN_PLL2_HSDIV4_CLKOUT | FOUTVCO_P/HSDIV4 | FOUTVCO_P default value is 2000MHz |
| 1 | MAIN_PLL2_HSDIV5_CLKOUT | FOUTPOSTDIV/HSDIV5 | FOUTPOSTDIV default value is 1000MHz |
| 1 | MAIN_PLL2_HSDIV6_CLKOUT | FOUTPOSTDIV/HSDIV6 | FOUTPOSTDIV default value is 1000MHz |
| 1 | MAIN_PLL2_HSDIV7_CLKOUT | Reserved | Reserved |
| 1 | MAIN_PLL2_HSDIV8_CLKOUT | FOUTPOSTDIV/HSDIV8 | FOUTPOSTDIV default value is 1000MHz |
| 1 | MAIN_PLL2_HSDIV9_CLKOUT | FOUTPOSTDIV/HSDIV9 | FOUTPOSTDIV default value is 1000MHz |
| PLL POSTDIV | HSDIV | Formula | Notes |
|---|---|---|---|
| 0 | MAIN_PLL4_HSDIV0_CLKOUT | FOUTVCO_P/HSDIV0 | FOUTVCO_P default value is 2539.296MHz |
| 0 | MAIN_PLL4_HSDIV1_CLKOUT | FOUTVCO_P/HSDIV1 | FOUTVCO_P default value is 2539.296MHz |
| 0 | MAIN_PLL4_HSDIV2_CLKOUT | FOUTVCO_P/HSDIV2 | FOUTVCO_P default value is 2539.296MHz |
| 0 | MAIN_PLL4_HSDIV3_CLKOUT | FOUTVCO_P/HSDIV3 | FOUTVCO_P default value is 2539.296MHz |
| PLL POSTDIV | HSDIV | Formula | Notes |
|---|---|---|---|
| 0 | MAIN_PLL7_HSDIV0_CLKOUT | FOUTVCO_P/HSDIV0 | FOUTVCO_P default value is 2550MHz |
| 0 | MAIN_PLL7_HSDIV1_CLKOUT | FOUTVCO_P/HSDIV1 | FOUTVCO_P default value is 2550MHz |
| PLL POSTDIV | HSDIV | Formula | Notes |
|---|---|---|---|
| 0 | MAIN_PLL14_HSDIV0_CLKOUT | FOUTVCO_P/HSDIV0 | FOUTVCO_P default value is 2400MHz |
| PLL POSTDIV | HSDIV | Formula | Notes |
|---|---|---|---|
| 0 | MAIN_PLL15_HSDIV0_CLKOUT | FOUTVCO_P/HSDIV0 | FOUTVCO_P default value is 2400MHz |
| 0 | MAIN_PLL15_HSDIV1_CLKOUT | FOUTVCO_P/HSDIV1 | FOUTVCO_P default value is 2400MHz |
| 0 | MAIN_PLL15_HSDIV2_CLKOUT | FOUTVCO_P/HSDIV2 | FOUTVCO_P default value is 2400MHz |