SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
A total of 8 destination channels are provided within the DMA for concurrent transfers from Tx per channel buffers to the various attached peripherals. Each Tx channel requires a single PSI-L thread. The Tx channels are allocated as follows:
| Tx DMA Channel | Function | Channel Type | Trigger Mode | Stream FIFO Address | Group FIFO Address |
|---|---|---|---|---|---|
| 8000 | ASRC0 Tx Ch 0 | ASRC | pulse | 000002D20000 | 000002D10000 |
| ASRC1 Tx Ch 0 | ASRC | pulse | 000002D60000 | 000002D50000 | |
| 8001 | ASRC0 Tx Ch 1 | ASRC | pulse | 000002D20000 | 000002D10000 |
| ASRC1 Tx Ch 1 | ASRC | pulse | 000002D60000 | 000002D50000 | |
| 8002 | ASRC0 Tx Ch 2 | ASRC | pulse | 000002D20000 | 000002D10000 |
| ASRC1 Tx Ch 2 | ASRC | pulse | 000002D60000 | 000002D50000 | |
| 8003 | ASRC0 Tx Ch 3 | ASRC | pulse | 000002D20000 | 000002D10000 |
| ASRC1 Tx Ch 3 | ASRC | pulse | 000002D60000 | 000002D50000 | |
| 8004 | ASRC0 Tx Ch 4 | ASRC | pulse | 000002D20000 | 000002D10000 |
| ASRC1 Tx Ch 4 | ASRC | pulse | 000002D60000 | 000002D50000 | |
| 8005 | ASRC0 Tx Ch 5 | ASRC | pulse | 000002D20000 | 000002D10000 |
| ASRC1 Tx Ch 5 | ASRC | pulse | 000002D60000 | 000002D50000 | |
| 8006 | ASRC0 Tx Ch 6 | ASRC | pulse | 000002D20000 | 000002D10000 |
| ASRC1 Tx Ch 6 | ASRC | pulse | 000002D60000 | 000002D50000 | |
| 8007 | ASRC0 Tx Ch 7 | ASRC | pulse | 000002D20000 | 000002D10000 |
| ASRC1 Tx Ch 7 | ASRC | pulse | 000002D60000 | 000002D50000 |