Integrated in MAIN domain is two different Flash Subsystem (FSS) providing access to external memory devices via Octal Serial Peripheral Interface (OSPI) along with encryption/decryption and in-line ECC protection. To summarize:
- OSPI_0 (FSS0)
- Supports TI OptiFlash, including XIP, for external flash devices
- OSPI_1 (FSS1)
- Supports HyperRAM based external RAM devices
- OR: Supports standard external flash device operation (i.e no OptiFlash)
- OR: Supports standard external RAM device operation
Separately, the FSS supports the following main features:
- FSS0
- 4Gbytes memory address support
- Firmware Over The Air (FOTA) accelerator functionality to support configuration and data interface access to flash Controller (OSPI)
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Support for single, dual, quad (Quad-SPI mode) or octal (on Octal-SPI0 only) I/O instructions
- Support for OptiFlash
- In Quad-SPI and Octal-SPI modes, support single data rate up to 166MHz SDR
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Memory mapped ‘direct’ mode of operation for performing flash data transfers and executing code from flash memory
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Software triggered 'indirect' mode of operation for performing low latency and non-processor intensive flash data transfers
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Local SRAM of configurable size to reduce advanced high-performance bus overhead and buffer flash data during indirect transfers
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Set of software advanced peripheral bus accessible flash control registers to perform any flash command, including data transfers up to 8-bytes at a time
- Additional addressable memory bank to accommodate more than 8-bytes at a time.
- Support for XIP, sometimes referred to as continuous mode.
- Programmable device sizes
- Programmable write protected regions to block system writes from taking effect
- Programmable delays between transactions
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Legacy mode allowing software direct access to low level transmit and receive FIFOs, bypassing the higher layer processes
- An independent reference clock to decouple bus clock from SPI clock – allows slow system clocks
- Programmable baud rate generator to generate OSPI clocks
- Features included to improve high speed read data capture mechanism
- Option to use adapted clocks or DQS to further improve read data capturing
- Programmable interrupt generation
- Up to four external device selects - OSPI and QSPI devices can be mixed
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Programmable data decoder, enables continuous addressing mode for each of the connected devices and auto-detection of boundaries between devices
- Supports BOOT mode
- Bidirectional CRC on Multiple-SPI
- Handling ECC errors for flash devices with embedded correction engine
- Full integration with PHY module dedicated to more flexible and power efficient transfers
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Supports RESET_OUT[1-0] and ECC_FAIL pins for external flash devices where ECC is checked on the flash
- Automatic Flash device status polling for programming operation (Auto HW Polling)
- FSS1
- Secondary OSPI supports
- 32-byte block (BC) operation
- ECC
- OSPIs support single, dual, quad, or octal SPI devices
- OSPIs support up to 4 devices
- HyperBus interface supports up to 2 devices
- The OSPIs and HyperBus interface have independent power management for low power operations
- Support for XIP, sometimes referred to as continuous mode.