SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register is used to configure the number of data blocks
Return to Summary Table
| Instance Name | Physical Address |
|---|---|
| MMCSD0 | 0FA0 0006h |
| 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 |
| XFER_BLK_CNT | |||||||
| R/W | |||||||
| 0h | |||||||
| 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 |
| XFER_BLK_CNT | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15:0 | XFER_BLK_CNT | R/W | 0h |
Host Controller Version 4.10 extends block count to 32-bit [Refer to Section 1.15].Selection of either 16-bit Block Count register or 32-bit Block Count register is defined as follows:
[1] If Host Version 4 Enable in the Host Control 2 register is set to 0 or 16-bit Block Count register is set to non-zero, 16-bit Block Count register is selected
[2] If Host Version 4 Enable is set to 1 and 16-bit Block Count register is set to zero, 32-bit Block Count register is selected.Use of 16-bit/32-bit Block Count register is enabled when Block Count Enable in the Transfer Mode register is set to 1 and is valid only for multiple block transfers. The Host Driver shall set this register to a value between 1 and the maximum block count.The Host Controller decrements the block count after each block transfer and stops when the count reaches zero. Setting the block count to 0 results in no data blocks is transferred.This register should be accessed only when no transaction is executing [i.e., after transactions are
stopped]. During data transfer,read operations on this register may return an invalid value and
write operations are ignored.
65535 3 2 1 0 |