SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
| Module Instance | Power Sleep Controller | Power Domain | Module Domain | Index | Default | Controllable | Dependencies |
|---|---|---|---|---|---|---|---|
| TIMER0 | MAIN_PSC0 | GP_CORE | LPSC_MAIN_IP0 | 18 | ON | YES | LPSC_MAIN_DM2MAIN_INFRA_ISO |
| TIMER1 | MAIN_PSC0 | GP_CORE | LPSC_MAIN_IP0 | 18 | ON | YES | LPSC_MAIN_DM2MAIN_INFRA_ISO |
| TIMER10 | MAIN_PSC0 | GP_CORE | LPSC_MAIN_IP0 | 18 | ON | YES | LPSC_MAIN_DM2MAIN_INFRA_ISO |
| TIMER11 | MAIN_PSC0 | GP_CORE | LPSC_MAIN_IP0 | 18 | ON | YES | LPSC_MAIN_DM2MAIN_INFRA_ISO |
| TIMER12 | MAIN_PSC0 | GP_CORE | LPSC_MAIN_IP0 | 18 | ON | YES | LPSC_MAIN_DM2MAIN_INFRA_ISO |
| TIMER13 | MAIN_PSC0 | GP_CORE | LPSC_MAIN_IP0 | 18 | ON | YES | LPSC_MAIN_DM2MAIN_INFRA_ISO |
| TIMER14 | MAIN_PSC0 | GP_CORE | LPSC_MAIN_IP0 | 18 | ON | YES | LPSC_MAIN_DM2MAIN_INFRA_ISO |
| TIMER15 | MAIN_PSC0 | GP_CORE | LPSC_MAIN_IP0 | 18 | ON | YES | LPSC_MAIN_DM2MAIN_INFRA_ISO |
| TIMER2 | MAIN_PSC0 | GP_CORE | LPSC_MAIN_IP0 | 18 | ON | YES | LPSC_MAIN_DM2MAIN_INFRA_ISO |
| TIMER3 | MAIN_PSC0 | GP_CORE | LPSC_MAIN_IP0 | 18 | ON | YES | LPSC_MAIN_DM2MAIN_INFRA_ISO |
| TIMER4 | MAIN_PSC0 | GP_CORE | LPSC_MAIN_IP0 | 18 | ON | YES | LPSC_MAIN_DM2MAIN_INFRA_ISO |
| TIMER5 | MAIN_PSC0 | GP_CORE | LPSC_MAIN_IP0 | 18 | ON | YES | LPSC_MAIN_DM2MAIN_INFRA_ISO |
| TIMER6 | MAIN_PSC0 | GP_CORE | LPSC_MAIN_IP0 | 18 | ON | YES | LPSC_MAIN_DM2MAIN_INFRA_ISO |
| TIMER7 | MAIN_PSC0 | GP_CORE | LPSC_MAIN_IP0 | 18 | ON | YES | LPSC_MAIN_DM2MAIN_INFRA_ISO |
| TIMER8 | MAIN_PSC0 | GP_CORE | LPSC_MAIN_IP0 | 18 | ON | YES | LPSC_MAIN_DM2MAIN_INFRA_ISO |
| TIMER9 | MAIN_PSC0 | GP_CORE | LPSC_MAIN_IP0 | 18 | ON | YES | LPSC_MAIN_DM2MAIN_INFRA_ISO |
| WKUP_TIMER0 | MAIN_PSC0 | GP_CORE | LPSC_MAIN_ALWAYSON | 0 | ON | NO | NONE |
| WKUP_TIMER1 | MAIN_PSC0 | GP_CORE | LPSC_MAIN_ALWAYSON | 0 | ON | NO | NONE |
| Module Instance | Source | Description |
|---|---|---|
| TIMER0 | MAIN_PSC0 | TIMER0 reset |
| TIMER1 | MAIN_PSC0 | TIMER1 reset |
| TIMER2 | MAIN_PSC0 | TIMER2 reset |
| TIMER3 | MAIN_PSC0 | TIMER3 reset |
| TIMER4 | MAIN_PSC0 | TIMER4 reset |
| TIMER5 | MAIN_PSC0 | TIMER5 reset |
| TIMER6 | MAIN_PSC0 | TIMER6 reset |
| TIMER7 | MAIN_PSC0 | TIMER7 reset |
| TIMER8 | MAIN_PSC0 | TIMER8 reset |
| TIMER9 | MAIN_PSC0 | TIMER9 reset |
| TIMER10 | MAIN_PSC0 | TIMER10 reset |
| TIMER11 | MAIN_PSC0 | TIMER11 reset |
| TIMER12 | MAIN_PSC0 | TIMER12 reset |
| TIMER13 | MAIN_PSC0 | TIMER13 reset |
| TIMER14 | MAIN_PSC0 | TIMER14 reset |
| TIMER15 | MAIN_PSC0 | TIMER15 reset |
| WKUP_TIMER0 | MAIN_PSC0 | WKUP_TIMER0 reset |
| WKUP_TIMER1 | MAIN_PSC0 | WKUP_TIMER1 reset |
| Module Instance | Module Interrupt Signal | Destination Interrupt Input | Destination | Description | Type |
|---|---|---|---|---|---|
| TIMER0 | TIMER0_intr_pend_0 | C7X256V0_CLEC_gic_spi_IN_152 | C7X256V0_CLEC | TIMER0 interrupt request | level |
| TIMER0 | TIMER0_intr_pend_0 | C7X256V1_CLEC_gic_spi_IN_152 | C7X256V1_CLEC | TIMER0 interrupt request | level |
| TIMER0 | TIMER0_intr_pend_0 | R5FSS0_CORE0_intr_IN_24 | R5FSS0_CORE0 | TIMER0 interrupt request | level |
| TIMER0 | TIMER0_intr_pend_0 | R5FSS0_CORE1_intr_IN_24 | R5FSS0_CORE1 | TIMER0 interrupt request | level |
| TIMER0 | TIMER0_intr_pend_0 | R5FSS1_CORE0_intr_IN_24 | R5FSS1_CORE0 | TIMER0 interrupt request | level |
| TIMER0 | TIMER0_intr_pend_0 | R5FSS1_CORE1_intr_IN_24 | R5FSS1_CORE1 | TIMER0 interrupt request | level |
| TIMER0 | TIMER0_timer_pwm_0 | MAIN_GPIO_INTROUTER0_in_IN_216 | MAIN_GPIO_INTROUTER0 | TIMER0 interrupt request | pulse |
| TIMER0 | TIMER0_timer_pwm_0 | TIMESYNC_INTROUTER0_in_IN_0 | TIMESYNC_INTROUTER0 | TIMER0 interrupt request | pulse |
| TIMER1 | TIMER1_intr_pend_0 | C7X256V0_CLEC_gic_spi_IN_153 | C7X256V0_CLEC | TIMER1 interrupt request | level |
| TIMER1 | TIMER1_intr_pend_0 | C7X256V1_CLEC_gic_spi_IN_153 | C7X256V1_CLEC | TIMER1 interrupt request | level |
| TIMER1 | TIMER1_intr_pend_0 | R5FSS0_CORE0_intr_IN_25 | R5FSS0_CORE0 | TIMER1 interrupt request | level |
| TIMER1 | TIMER1_intr_pend_0 | R5FSS0_CORE1_intr_IN_25 | R5FSS0_CORE1 | TIMER1 interrupt request | level |
| TIMER1 | TIMER1_intr_pend_0 | R5FSS1_CORE0_intr_IN_25 | R5FSS1_CORE0 | TIMER1 interrupt request | level |
| TIMER1 | TIMER1_intr_pend_0 | R5FSS1_CORE1_intr_IN_25 | R5FSS1_CORE1 | TIMER1 interrupt request | level |
| TIMER1 | TIMER1_timer_pwm_0 | MAIN_GPIO_INTROUTER0_in_IN_217 | MAIN_GPIO_INTROUTER0 | TIMER1 interrupt request | pulse |
| TIMER1 | TIMER1_timer_pwm_0 | TIMESYNC_INTROUTER0_in_IN_1 | TIMESYNC_INTROUTER0 | TIMER1 interrupt request | pulse |
| TIMER2 | TIMER2_intr_pend_0 | C7X256V0_CLEC_gic_spi_IN_154 | C7X256V0_CLEC | TIMER2 interrupt request | level |
| TIMER2 | TIMER2_intr_pend_0 | C7X256V1_CLEC_gic_spi_IN_154 | C7X256V1_CLEC | TIMER2 interrupt request | level |
| TIMER2 | TIMER2_intr_pend_0 | R5FSS0_CORE0_intr_IN_26 | R5FSS0_CORE0 | TIMER2 interrupt request | level |
| TIMER2 | TIMER2_intr_pend_0 | R5FSS0_CORE1_intr_IN_26 | R5FSS0_CORE1 | TIMER2 interrupt request | level |
| TIMER2 | TIMER2_intr_pend_0 | R5FSS1_CORE0_intr_IN_26 | R5FSS1_CORE0 | TIMER2 interrupt request | level |
| TIMER2 | TIMER2_intr_pend_0 | R5FSS1_CORE1_intr_IN_26 | R5FSS1_CORE1 | TIMER2 interrupt request | level |
| TIMER2 | TIMER2_timer_pwm_0 | MAIN_GPIO_INTROUTER0_in_IN_218 | MAIN_GPIO_INTROUTER0 | TIMER2 interrupt request | pulse |
| TIMER2 | TIMER2_timer_pwm_0 | TIMESYNC_INTROUTER0_in_IN_2 | TIMESYNC_INTROUTER0 | TIMER2 interrupt request | pulse |
| TIMER3 | TIMER3_intr_pend_0 | C7X256V0_CLEC_gic_spi_IN_155 | C7X256V0_CLEC | TIMER3 interrupt request | level |
| TIMER3 | TIMER3_intr_pend_0 | C7X256V1_CLEC_gic_spi_IN_155 | C7X256V1_CLEC | TIMER3 interrupt request | level |
| TIMER3 | TIMER3_intr_pend_0 | R5FSS0_CORE0_intr_IN_27 | R5FSS0_CORE0 | TIMER3 interrupt request | level |
| TIMER3 | TIMER3_intr_pend_0 | R5FSS0_CORE1_intr_IN_27 | R5FSS0_CORE1 | TIMER3 interrupt request | level |
| TIMER3 | TIMER3_intr_pend_0 | R5FSS1_CORE0_intr_IN_27 | R5FSS1_CORE0 | TIMER3 interrupt request | level |
| TIMER3 | TIMER3_intr_pend_0 | R5FSS1_CORE1_intr_IN_27 | R5FSS1_CORE1 | TIMER3 interrupt request | level |
| TIMER3 | TIMER3_timer_pwm_0 | MAIN_GPIO_INTROUTER0_in_IN_219 | MAIN_GPIO_INTROUTER0 | TIMER3 interrupt request | pulse |
| TIMER3 | TIMER3_timer_pwm_0 | TIMESYNC_INTROUTER0_in_IN_3 | TIMESYNC_INTROUTER0 | TIMER3 interrupt request | pulse |
| TIMER4 | TIMER4_intr_pend_0 | C7X256V0_CLEC_gic_spi_IN_156 | C7X256V0_CLEC | TIMER4 interrupt request | level |
| TIMER4 | TIMER4_intr_pend_0 | C7X256V1_CLEC_gic_spi_IN_156 | C7X256V1_CLEC | TIMER4 interrupt request | level |
| TIMER4 | TIMER4_intr_pend_0 | R5FSS0_CORE0_intr_IN_28 | R5FSS0_CORE0 | TIMER4 interrupt request | level |
| TIMER4 | TIMER4_intr_pend_0 | R5FSS0_CORE1_intr_IN_28 | R5FSS0_CORE1 | TIMER4 interrupt request | level |
| TIMER4 | TIMER4_intr_pend_0 | R5FSS1_CORE0_intr_IN_28 | R5FSS1_CORE0 | TIMER4 interrupt request | level |
| TIMER4 | TIMER4_intr_pend_0 | R5FSS1_CORE1_intr_IN_28 | R5FSS1_CORE1 | TIMER4 interrupt request | level |
| TIMER4 | TIMER4_timer_pwm_0 | MAIN_GPIO_INTROUTER0_in_IN_220 | MAIN_GPIO_INTROUTER0 | TIMER4 interrupt request | pulse |
| TIMER4 | TIMER4_timer_pwm_0 | TIMESYNC_INTROUTER0_in_IN_4 | TIMESYNC_INTROUTER0 | TIMER4 interrupt request | pulse |
| TIMER5 | TIMER5_intr_pend_0 | C7X256V0_CLEC_gic_spi_IN_157 | C7X256V0_CLEC | TIMER5 interrupt request | level |
| TIMER5 | TIMER5_intr_pend_0 | C7X256V1_CLEC_gic_spi_IN_157 | C7X256V1_CLEC | TIMER5 interrupt request | level |
| TIMER5 | TIMER5_intr_pend_0 | R5FSS0_CORE0_intr_IN_29 | R5FSS0_CORE0 | TIMER5 interrupt request | level |
| TIMER5 | TIMER5_intr_pend_0 | R5FSS0_CORE1_intr_IN_29 | R5FSS0_CORE1 | TIMER5 interrupt request | level |
| TIMER5 | TIMER5_intr_pend_0 | R5FSS1_CORE0_intr_IN_29 | R5FSS1_CORE0 | TIMER5 interrupt request | level |
| TIMER5 | TIMER5_intr_pend_0 | R5FSS1_CORE1_intr_IN_29 | R5FSS1_CORE1 | TIMER5 interrupt request | level |
| TIMER5 | TIMER5_timer_pwm_0 | MAIN_GPIO_INTROUTER0_in_IN_221 | MAIN_GPIO_INTROUTER0 | TIMER5 interrupt request | pulse |
| TIMER5 | TIMER5_timer_pwm_0 | TIMESYNC_INTROUTER0_in_IN_5 | TIMESYNC_INTROUTER0 | TIMER5 interrupt request | pulse |
| TIMER6 | TIMER6_intr_pend_0 | C7X256V0_CLEC_gic_spi_IN_158 | C7X256V0_CLEC | TIMER6 interrupt request | level |
| TIMER6 | TIMER6_intr_pend_0 | C7X256V1_CLEC_gic_spi_IN_158 | C7X256V1_CLEC | TIMER6 interrupt request | level |
| TIMER6 | TIMER6_intr_pend_0 | R5FSS0_CORE0_intr_IN_22 | R5FSS0_CORE0 | TIMER6 interrupt request | level |
| TIMER6 | TIMER6_intr_pend_0 | R5FSS0_CORE1_intr_IN_22 | R5FSS0_CORE1 | TIMER6 interrupt request | level |
| TIMER6 | TIMER6_intr_pend_0 | R5FSS1_CORE0_intr_IN_22 | R5FSS1_CORE0 | TIMER6 interrupt request | level |
| TIMER6 | TIMER6_intr_pend_0 | R5FSS1_CORE1_intr_IN_22 | R5FSS1_CORE1 | TIMER6 interrupt request | level |
| TIMER6 | TIMER6_timer_pwm_0 | MAIN_GPIO_INTROUTER0_in_IN_222 | MAIN_GPIO_INTROUTER0 | TIMER6 interrupt request | pulse |
| TIMER6 | TIMER6_timer_pwm_0 | TIMESYNC_INTROUTER0_in_IN_6 | TIMESYNC_INTROUTER0 | TIMER6 interrupt request | pulse |
| TIMER7 | TIMER7_intr_pend_0 | C7X256V0_CLEC_gic_spi_IN_159 | C7X256V0_CLEC | TIMER7 interrupt request | level |
| TIMER7 | TIMER7_intr_pend_0 | C7X256V1_CLEC_gic_spi_IN_159 | C7X256V1_CLEC | TIMER7 interrupt request | level |
| TIMER7 | TIMER7_intr_pend_0 | R5FSS0_CORE0_intr_IN_23 | R5FSS0_CORE0 | TIMER7 interrupt request | level |
| TIMER7 | TIMER7_intr_pend_0 | R5FSS0_CORE1_intr_IN_23 | R5FSS0_CORE1 | TIMER7 interrupt request | level |
| TIMER7 | TIMER7_intr_pend_0 | R5FSS1_CORE0_intr_IN_23 | R5FSS1_CORE0 | TIMER7 interrupt request | level |
| TIMER7 | TIMER7_intr_pend_0 | R5FSS1_CORE1_intr_IN_23 | R5FSS1_CORE1 | TIMER7 interrupt request | level |
| TIMER7 | TIMER7_timer_pwm_0 | MAIN_GPIO_INTROUTER0_in_IN_223 | MAIN_GPIO_INTROUTER0 | TIMER7 interrupt request | pulse |
| TIMER7 | TIMER7_timer_pwm_0 | TIMESYNC_INTROUTER0_in_IN_7 | TIMESYNC_INTROUTER0 | TIMER7 interrupt request | pulse |
| TIMER8 | TIMER8_intr_pend_0 | C7X256V0_CLEC_gic_spi_IN_64 | C7X256V0_CLEC | TIMER8 interrupt request | level |
| TIMER8 | TIMER8_intr_pend_0 | C7X256V1_CLEC_gic_spi_IN_64 | C7X256V1_CLEC | TIMER8 interrupt request | level |
| TIMER8 | TIMER8_intr_pend_0 | R5FSS0_CORE0_intr_IN_264 | R5FSS0_CORE0 | TIMER8 interrupt request | level |
| TIMER8 | TIMER8_intr_pend_0 | R5FSS0_CORE1_intr_IN_264 | R5FSS0_CORE1 | TIMER8 interrupt request | level |
| TIMER8 | TIMER8_intr_pend_0 | R5FSS1_CORE0_intr_IN_264 | R5FSS1_CORE0 | TIMER8 interrupt request | level |
| TIMER8 | TIMER8_intr_pend_0 | R5FSS1_CORE1_intr_IN_264 | R5FSS1_CORE1 | TIMER8 interrupt request | level |
| TIMER8 | TIMER8_timer_pwm_0 | MAIN_GPIO_INTROUTER0_in_IN_224 | MAIN_GPIO_INTROUTER0 | TIMER8 interrupt request | pulse |
| TIMER8 | TIMER8_timer_pwm_0 | TIMESYNC_INTROUTER0_in_IN_8 | TIMESYNC_INTROUTER0 | TIMER8 interrupt request | pulse |
| TIMER9 | TIMER9_intr_pend_0 | C7X256V0_CLEC_gic_spi_IN_65 | C7X256V0_CLEC | TIMER9 interrupt request | level |
| TIMER9 | TIMER9_intr_pend_0 | C7X256V1_CLEC_gic_spi_IN_65 | C7X256V1_CLEC | TIMER9 interrupt request | level |
| TIMER9 | TIMER9_intr_pend_0 | R5FSS0_CORE0_intr_IN_265 | R5FSS0_CORE0 | TIMER9 interrupt request | level |
| TIMER9 | TIMER9_intr_pend_0 | R5FSS0_CORE1_intr_IN_265 | R5FSS0_CORE1 | TIMER9 interrupt request | level |
| TIMER9 | TIMER9_intr_pend_0 | R5FSS1_CORE0_intr_IN_265 | R5FSS1_CORE0 | TIMER9 interrupt request | level |
| TIMER9 | TIMER9_intr_pend_0 | R5FSS1_CORE1_intr_IN_265 | R5FSS1_CORE1 | TIMER9 interrupt request | level |
| TIMER9 | TIMER9_timer_pwm_0 | MAIN_GPIO_INTROUTER0_in_IN_225 | MAIN_GPIO_INTROUTER0 | TIMER9 interrupt request | pulse |
| TIMER10 | TIMER10_intr_pend_0 | C7X256V0_CLEC_gic_spi_IN_66 | C7X256V0_CLEC | TIMER10 interrupt request | level |
| TIMER10 | TIMER10_intr_pend_0 | C7X256V1_CLEC_gic_spi_IN_66 | C7X256V1_CLEC | TIMER10 interrupt request | level |
| TIMER10 | TIMER10_intr_pend_0 | R5FSS0_CORE0_intr_IN_266 | R5FSS0_CORE0 | TIMER10 interrupt request | level |
| TIMER10 | TIMER10_intr_pend_0 | R5FSS0_CORE1_intr_IN_266 | R5FSS0_CORE1 | TIMER10 interrupt request | level |
| TIMER10 | TIMER10_intr_pend_0 | R5FSS1_CORE0_intr_IN_266 | R5FSS1_CORE0 | TIMER10 interrupt request | level |
| TIMER10 | TIMER10_intr_pend_0 | R5FSS1_CORE1_intr_IN_266 | R5FSS1_CORE1 | TIMER10 interrupt request | level |
| TIMER10 | TIMER10_timer_pwm_0 | MAIN_GPIO_INTROUTER0_in_IN_226 | MAIN_GPIO_INTROUTER0 | TIMER10 interrupt request | pulse |
| TIMER11 | TIMER11_intr_pend_0 | C7X256V0_CLEC_gic_spi_IN_67 | C7X256V0_CLEC | TIMER11 interrupt request | level |
| TIMER11 | TIMER11_intr_pend_0 | C7X256V1_CLEC_gic_spi_IN_67 | C7X256V1_CLEC | TIMER11 interrupt request | level |
| TIMER11 | TIMER11_intr_pend_0 | R5FSS0_CORE0_intr_IN_267 | R5FSS0_CORE0 | TIMER11 interrupt request | level |
| TIMER11 | TIMER11_intr_pend_0 | R5FSS0_CORE1_intr_IN_267 | R5FSS0_CORE1 | TIMER11 interrupt request | level |
| TIMER11 | TIMER11_intr_pend_0 | R5FSS1_CORE0_intr_IN_267 | R5FSS1_CORE0 | TIMER11 interrupt request | level |
| TIMER11 | TIMER11_intr_pend_0 | R5FSS1_CORE1_intr_IN_267 | R5FSS1_CORE1 | TIMER11 interrupt request | level |
| TIMER11 | TIMER11_timer_pwm_0 | MAIN_GPIO_INTROUTER0_in_IN_227 | MAIN_GPIO_INTROUTER0 | TIMER11 interrupt request | pulse |
| TIMER12 | TIMER12_intr_pend_0 | C7X256V0_CLEC_gic_spi_IN_68 | C7X256V0_CLEC | TIMER12 interrupt request | level |
| TIMER12 | TIMER12_intr_pend_0 | C7X256V1_CLEC_gic_spi_IN_68 | C7X256V1_CLEC | TIMER12 interrupt request | level |
| TIMER12 | TIMER12_intr_pend_0 | R5FSS0_CORE0_intr_IN_268 | R5FSS0_CORE0 | TIMER12 interrupt request | level |
| TIMER12 | TIMER12_intr_pend_0 | R5FSS0_CORE1_intr_IN_268 | R5FSS0_CORE1 | TIMER12 interrupt request | level |
| TIMER12 | TIMER12_intr_pend_0 | R5FSS1_CORE0_intr_IN_268 | R5FSS1_CORE0 | TIMER12 interrupt request | level |
| TIMER12 | TIMER12_intr_pend_0 | R5FSS1_CORE1_intr_IN_268 | R5FSS1_CORE1 | TIMER12 interrupt request | level |
| TIMER12 | TIMER12_timer_pwm_0 | MAIN_GPIO_INTROUTER0_in_IN_228 | MAIN_GPIO_INTROUTER0 | TIMER12 interrupt request | pulse |
| TIMER13 | TIMER13_intr_pend_0 | C7X256V0_CLEC_gic_spi_IN_69 | C7X256V0_CLEC | TIMER13 interrupt request | level |
| TIMER13 | TIMER13_intr_pend_0 | C7X256V1_CLEC_gic_spi_IN_69 | C7X256V1_CLEC | TIMER13 interrupt request | level |
| TIMER13 | TIMER13_intr_pend_0 | R5FSS0_CORE0_intr_IN_269 | R5FSS0_CORE0 | TIMER13 interrupt request | level |
| TIMER13 | TIMER13_intr_pend_0 | R5FSS0_CORE1_intr_IN_269 | R5FSS0_CORE1 | TIMER13 interrupt request | level |
| TIMER13 | TIMER13_intr_pend_0 | R5FSS1_CORE0_intr_IN_269 | R5FSS1_CORE0 | TIMER13 interrupt request | level |
| TIMER13 | TIMER13_intr_pend_0 | R5FSS1_CORE1_intr_IN_269 | R5FSS1_CORE1 | TIMER13 interrupt request | level |
| TIMER13 | TIMER13_timer_pwm_0 | MAIN_GPIO_INTROUTER0_in_IN_229 | MAIN_GPIO_INTROUTER0 | TIMER13 interrupt request | pulse |
| TIMER14 | TIMER14_intr_pend_0 | C7X256V0_CLEC_gic_spi_IN_70 | C7X256V0_CLEC | TIMER14 interrupt request | level |
| TIMER14 | TIMER14_intr_pend_0 | C7X256V1_CLEC_gic_spi_IN_70 | C7X256V1_CLEC | TIMER14 interrupt request | level |
| TIMER14 | TIMER14_intr_pend_0 | R5FSS0_CORE0_intr_IN_270 | R5FSS0_CORE0 | TIMER14 interrupt request | level |
| TIMER14 | TIMER14_intr_pend_0 | R5FSS0_CORE1_intr_IN_270 | R5FSS0_CORE1 | TIMER14 interrupt request | level |
| TIMER14 | TIMER14_intr_pend_0 | R5FSS1_CORE0_intr_IN_270 | R5FSS1_CORE0 | TIMER14 interrupt request | level |
| TIMER14 | TIMER14_intr_pend_0 | R5FSS1_CORE1_intr_IN_270 | R5FSS1_CORE1 | TIMER14 interrupt request | level |
| TIMER14 | TIMER14_timer_pwm_0 | MAIN_GPIO_INTROUTER0_in_IN_230 | MAIN_GPIO_INTROUTER0 | TIMER14 interrupt request | pulse |
| TIMER15 | TIMER15_intr_pend_0 | C7X256V0_CLEC_gic_spi_IN_71 | C7X256V0_CLEC | TIMER15 interrupt request | level |
| TIMER15 | TIMER15_intr_pend_0 | C7X256V1_CLEC_gic_spi_IN_71 | C7X256V1_CLEC | TIMER15 interrupt request | level |
| TIMER15 | TIMER15_intr_pend_0 | R5FSS0_CORE0_intr_IN_271 | R5FSS0_CORE0 | TIMER15 interrupt request | level |
| TIMER15 | TIMER15_intr_pend_0 | R5FSS0_CORE1_intr_IN_271 | R5FSS0_CORE1 | TIMER15 interrupt request | level |
| TIMER15 | TIMER15_intr_pend_0 | R5FSS1_CORE0_intr_IN_271 | R5FSS1_CORE0 | TIMER15 interrupt request | level |
| TIMER15 | TIMER15_intr_pend_0 | R5FSS1_CORE1_intr_IN_271 | R5FSS1_CORE1 | TIMER15 interrupt request | level |
| TIMER15 | TIMER15_timer_pwm_0 | MAIN_GPIO_INTROUTER0_in_IN_231 | MAIN_GPIO_INTROUTER0 | TIMER15 interrupt request | pulse |
| WKUP_TIMER0 | WKUP_TIMER0_intr_pend_0 | WKUP_R5FSS0_CORE0_intr_IN_138 | WKUP_R5FSS0_CORE0 | WKUP_TIMER0 interrupt request | level |
| WKUP_TIMER0 | WKUP_TIMER0_timer_clkstop_wakeup_0 | WKUP_R5FSS0_CORE0_intr_IN_28 | WKUP_R5FSS0_CORE0 | WKUP_TIMER0 interrupt request | level |
| WKUP_TIMER0 | WKUP_TIMER0_timer_pwm_0 | MAIN_GPIO_INTROUTER0_in_IN_214 | MAIN_GPIO_INTROUTER0 | WKUP_TIMER0 interrupt request | pulse |
| WKUP_TIMER1 | WKUP_TIMER1_intr_pend_0 | WKUP_R5FSS0_CORE0_intr_IN_139 | WKUP_R5FSS0_CORE0 | WKUP_TIMER1 interrupt request | level |
| WKUP_TIMER1 | WKUP_TIMER1_timer_clkstop_wakeup_0 | WKUP_R5FSS0_CORE0_intr_IN_29 | WKUP_R5FSS0_CORE0 | WKUP_TIMER1 interrupt request | level |
| WKUP_TIMER1 | WKUP_TIMER1_timer_pwm_0 | MAIN_GPIO_INTROUTER0_in_IN_215 | MAIN_GPIO_INTROUTER0 | WKUP_TIMER1 interrupt request | pulse |
| Module Instance | Module Clock Input | Source Clock Signal | Source Control Register | Description |
|---|---|---|---|---|
| TIMER0 | TIMER_ICLK | MAIN_SYSCLK0/4 | TIMER0 Interface Clock | |
| TIMER_FCLK | HFOSC0_CLKOUT | TIMER0_CLKSEL[3:0] | TIMER0 Functional Clock | |
| DEVICE_CLKOUT_32K | TIMER0_CLKSEL[3:0] | |||
| DEVICE_CLKOUT_32K_CTRL[1:0] | ||||
| MAIN_SYSCLK0/2 | TIMER0_CLKSEL[3:0] | |||
| MAIN_PBIST_CLK | TIMER0_CLKSEL[3:0] | |||
| MAIN_PLL2_HSDIV5_CLKOUT | TIMER0_CLKSEL[3:0] | |||
| CPSW_CLKSEL[2:0] | ||||
| MAIN_PLL0_HSDIV6_CLKOUT | TIMER0_CLKSEL[3:0] | |||
| CPSW_CLKSEL[2:0] | ||||
| CP_GEMAC_CPTS_REF_CLK | TIMER0_CLKSEL[3:0] | |||
| CPSW_CLKSEL[2:0] | ||||
| MCU_EXT_REFCLK0 | TIMER0_CLKSEL[3:0] | |||
| CPSW_CLKSEL[2:0] | ||||
| EXT_REFCLK1 | TIMER0_CLKSEL[3:0] | |||
| CPSW_CLKSEL[2:0] | ||||
| MAIN_PLL4_HSDIV1_CLKOUT | TIMER0_CLKSEL[3:0] | |||
| CPSW_CLKSEL[2:0] | ||||
| MAIN_SYSCLK0 | TIMER0_CLKSEL[3:0] | |||
| CPSW_CLKSEL[2:0] | ||||
| MAIN_PLL2_HSDIV1_CLKOUT/10 | TIMER0_CLKSEL[3:0] | |||
| MAIN_PLL2_HSDIV1_CLKOUT/2 | TIMER0_CLKSEL[3:0] | |||
| MAIN_PLL2_HSDIV1_CLKOUT | TIMER0_CLKSEL[3:0] | |||
| MAIN_PLL2_HSDIV1_CLKOUT/5 | TIMER0_CLKSEL[3:0] | |||
| MAIN_PLL2_HSDIV1_CLKOUT/50 | TIMER0_CLKSEL[3:0] | |||
| MAIN_PLL4_HSDIV2_CLKOUT | TIMER0_CLKSEL[3:0] | |||
| MAIN_PLL0_HSDIV7_CLKOUT | TIMER0_CLKSEL[3:0] | |||
| CLK_12M_RC | TIMER0_CLKSEL[3:0] | |||
| CP_GEMAC_CPTS_REF_CLK | TIMER0_CLKSEL[3:0] | |||
| MAIN_PLL1_HSDIV3_CLKOUT | TIMER0_CLKSEL[3:0] | |||
| MAIN_PLL2_HSDIV6_CLKOUT | TIMER0_CLKSEL[3:0] | |||
| TIMER1 | TIMER_ICLK | MAIN_SYSCLK0/4 | TIMER1 Interface Clock | |
| TIMER_FCLK | HFOSC0_CLKOUT | TIMER1_CTRL[8:8] | TIMER1 Functional Clock | |
| TIMER1_CLKSEL[3:0] | ||||
| DEVICE_CLKOUT_32K | TIMER1_CTRL[8:8] | |||
| TIMER1_CLKSEL[3:0] | ||||
| DEVICE_CLKOUT_32K_CTRL[1:0] | ||||
| MAIN_SYSCLK0/2 | TIMER1_CTRL[8:8] | |||
| TIMER1_CLKSEL[3:0] | ||||
| MAIN_PBIST_CLK | TIMER1_CTRL[8:8] | |||
| TIMER1_CLKSEL[3:0] | ||||
| MAIN_PLL2_HSDIV5_CLKOUT | TIMER1_CTRL[8:8] | |||
| TIMER1_CLKSEL[3:0] | ||||
| CPSW_CLKSEL[2:0] | ||||
| MAIN_PLL0_HSDIV6_CLKOUT | TIMER1_CTRL[8:8] | |||
| TIMER1_CLKSEL[3:0] | ||||
| CPSW_CLKSEL[2:0] | ||||
| CP_GEMAC_CPTS_REF_CLK | TIMER1_CTRL[8:8] | |||
| TIMER1_CLKSEL[3:0] | ||||
| CPSW_CLKSEL[2:0] | ||||
| MCU_EXT_REFCLK0 | TIMER1_CTRL[8:8] | |||
| TIMER1_CLKSEL[3:0] | ||||
| CPSW_CLKSEL[2:0] | ||||
| EXT_REFCLK1 | TIMER1_CTRL[8:8] | |||
| TIMER1_CLKSEL[3:0] | ||||
| CPSW_CLKSEL[2:0] | ||||
| MAIN_PLL4_HSDIV1_CLKOUT | TIMER1_CTRL[8:8] | |||
| TIMER1_CLKSEL[3:0] | ||||
| CPSW_CLKSEL[2:0] | ||||
| MAIN_SYSCLK0 | TIMER1_CTRL[8:8] | |||
| TIMER1_CLKSEL[3:0] | ||||
| CPSW_CLKSEL[2:0] | ||||
| MAIN_PLL2_HSDIV1_CLKOUT/10 | TIMER1_CTRL[8:8] | |||
| TIMER1_CLKSEL[3:0] | ||||
| MAIN_PLL2_HSDIV1_CLKOUT | TIMER1_CTRL[8:8] | |||
| TIMER1_CLKSEL[3:0] | ||||
| MAIN_PLL2_HSDIV1_CLKOUT/5 | TIMER1_CTRL[8:8] | |||
| TIMER1_CLKSEL[3:0] | ||||
| MAIN_PLL2_HSDIV1_CLKOUT/50 | TIMER1_CTRL[8:8] | |||
| TIMER1_CLKSEL[3:0] | ||||
| MAIN_PLL4_HSDIV2_CLKOUT | TIMER1_CTRL[8:8] | |||
| TIMER1_CLKSEL[3:0] | ||||
| MAIN_PLL0_HSDIV7_CLKOUT | TIMER1_CTRL[8:8] | |||
| TIMER1_CLKSEL[3:0] | ||||
| CLK_12M_RC | TIMER1_CTRL[8:8] | |||
| TIMER1_CLKSEL[3:0] | ||||
| MCU_EXT_REFCLK0 | TIMER1_CLKSEL[3:0] | |||
| CP_GEMAC_CPTS_REF_CLK | TIMER1_CTRL[8:8] | |||
| TIMER1_CLKSEL[3:0] | ||||
| MAIN_PLL1_HSDIV3_CLKOUT | TIMER1_CTRL[8:8] | |||
| TIMER1_CLKSEL[3:0] | ||||
| MAIN_PLL2_HSDIV6_CLKOUT | TIMER1_CTRL[8:8] | |||
| TIMER1_CLKSEL[3:0] | ||||
| MAIN_SYSCLK0/4 | TIMER1_CTRL[8:8] | |||
| TIMER2 | TIMER_ICLK | MAIN_SYSCLK0/4 | TIMER2 Interface Clock | |
| TIMER_FCLK | HFOSC0_CLKOUT | TIMER2_CLKSEL[3:0] | TIMER2 Functional Clock | |
| DEVICE_CLKOUT_32K | TIMER2_CLKSEL[3:0] | |||
| DEVICE_CLKOUT_32K_CTRL[1:0] | ||||
| MAIN_SYSCLK0/2 | TIMER2_CLKSEL[3:0] | |||
| MAIN_PBIST_CLK | TIMER2_CLKSEL[3:0] | |||
| MAIN_PLL2_HSDIV5_CLKOUT | TIMER2_CLKSEL[3:0] | |||
| CPSW_CLKSEL[2:0] | ||||
| MAIN_PLL0_HSDIV6_CLKOUT | TIMER2_CLKSEL[3:0] | |||
| CPSW_CLKSEL[2:0] | ||||
| CP_GEMAC_CPTS_REF_CLK | TIMER2_CLKSEL[3:0] | |||
| CPSW_CLKSEL[2:0] | ||||
| MCU_EXT_REFCLK0 | TIMER2_CLKSEL[3:0] | |||
| CPSW_CLKSEL[2:0] | ||||
| EXT_REFCLK1 | TIMER2_CLKSEL[3:0] | |||
| CPSW_CLKSEL[2:0] | ||||
| MAIN_PLL4_HSDIV1_CLKOUT | TIMER2_CLKSEL[3:0] | |||
| CPSW_CLKSEL[2:0] | ||||
| MAIN_SYSCLK0 | TIMER2_CLKSEL[3:0] | |||
| CPSW_CLKSEL[2:0] | ||||
| MAIN_PLL2_HSDIV1_CLKOUT/10 | TIMER2_CLKSEL[3:0] | |||
| MAIN_PLL2_HSDIV1_CLKOUT/2 | TIMER2_CLKSEL[3:0] | |||
| MAIN_PLL2_HSDIV1_CLKOUT | TIMER2_CLKSEL[3:0] | |||
| MAIN_PLL2_HSDIV1_CLKOUT/5 | TIMER2_CLKSEL[3:0] | |||
| MAIN_PLL2_HSDIV1_CLKOUT/50 | TIMER2_CLKSEL[3:0] | |||
| MAIN_PLL4_HSDIV2_CLKOUT | TIMER2_CLKSEL[3:0] | |||
| MAIN_PLL0_HSDIV7_CLKOUT | TIMER2_CLKSEL[3:0] | |||
| CLK_12M_RC | TIMER2_CLKSEL[3:0] | |||
| CP_GEMAC_CPTS_REF_CLK | TIMER2_CLKSEL[3:0] | |||
| MAIN_PLL1_HSDIV3_CLKOUT | TIMER2_CLKSEL[3:0] | |||
| MAIN_PLL2_HSDIV6_CLKOUT | TIMER2_CLKSEL[3:0] | |||
| TIMER3 | TIMER_ICLK | MAIN_SYSCLK0/4 | TIMER3 Interface Clock | |
| TIMER_FCLK | HFOSC0_CLKOUT | TIMER3_CTRL[8:8] | TIMER3 Functional Clock | |
| TIMER3_CLKSEL[3:0] | ||||
| DEVICE_CLKOUT_32K | TIMER3_CTRL[8:8] | |||
| TIMER3_CLKSEL[3:0] | ||||
| DEVICE_CLKOUT_32K_CTRL[1:0] | ||||
| MAIN_SYSCLK0/2 | TIMER3_CTRL[8:8] | |||
| TIMER3_CLKSEL[3:0] | ||||
| MAIN_PBIST_CLK | TIMER3_CTRL[8:8] | |||
| TIMER3_CLKSEL[3:0] | ||||
| MAIN_PLL2_HSDIV5_CLKOUT | TIMER3_CTRL[8:8] | |||
| TIMER3_CLKSEL[3:0] | ||||
| CPSW_CLKSEL[2:0] | ||||
| MAIN_PLL0_HSDIV6_CLKOUT | TIMER3_CTRL[8:8] | |||
| TIMER3_CLKSEL[3:0] | ||||
| CPSW_CLKSEL[2:0] | ||||
| CP_GEMAC_CPTS_REF_CLK | TIMER3_CTRL[8:8] | |||
| TIMER3_CLKSEL[3:0] | ||||
| CPSW_CLKSEL[2:0] | ||||
| MCU_EXT_REFCLK0 | TIMER3_CTRL[8:8] | |||
| TIMER3_CLKSEL[3:0] | ||||
| CPSW_CLKSEL[2:0] | ||||
| EXT_REFCLK1 | TIMER3_CTRL[8:8] | |||
| TIMER3_CLKSEL[3:0] | ||||
| CPSW_CLKSEL[2:0] | ||||
| MAIN_PLL4_HSDIV1_CLKOUT | TIMER3_CTRL[8:8] | |||
| TIMER3_CLKSEL[3:0] | ||||
| CPSW_CLKSEL[2:0] | ||||
| MAIN_SYSCLK0 | TIMER3_CTRL[8:8] | |||
| TIMER3_CLKSEL[3:0] | ||||
| CPSW_CLKSEL[2:0] | ||||
| MAIN_PLL2_HSDIV1_CLKOUT/10 | TIMER3_CTRL[8:8] | |||
| TIMER3_CLKSEL[3:0] | ||||
| MAIN_PLL2_HSDIV1_CLKOUT/2 | TIMER3_CTRL[8:8] | |||
| TIMER3_CLKSEL[3:0] | ||||
| MAIN_PLL2_HSDIV1_CLKOUT | TIMER3_CTRL[8:8] | |||
| TIMER3_CLKSEL[3:0] | ||||
| MAIN_PLL2_HSDIV1_CLKOUT/5 | TIMER3_CTRL[8:8] | |||
| TIMER3_CLKSEL[3:0] | ||||
| MAIN_PLL2_HSDIV1_CLKOUT/50 | TIMER3_CTRL[8:8] | |||
| TIMER3_CLKSEL[3:0] | ||||
| MAIN_PLL4_HSDIV2_CLKOUT | TIMER3_CTRL[8:8] | |||
| TIMER3_CLKSEL[3:0] | ||||
| MAIN_PLL0_HSDIV7_CLKOUT | TIMER3_CTRL[8:8] | |||
| TIMER3_CLKSEL[3:0] | ||||
| CLK_12M_RC | TIMER3_CTRL[8:8] | |||
| TIMER3_CLKSEL[3:0] | ||||
| CP_GEMAC_CPTS_REF_CLK | TIMER3_CTRL[8:8] | |||
| TIMER3_CLKSEL[3:0] | ||||
| MAIN_PLL1_HSDIV3_CLKOUT | TIMER3_CTRL[8:8] | |||
| TIMER3_CLKSEL[3:0] | ||||
| MAIN_PLL2_HSDIV6_CLKOUT | TIMER3_CTRL[8:8] | |||
| TIMER3_CLKSEL[3:0] | ||||
| MAIN_SYSCLK0/4 | TIMER3_CTRL[8:8] | |||
| TIMER4 | TIMER_ICLK | MAIN_SYSCLK0/4 | TIMER4 Interface Clock | |
| TIMER_FCLK | HFOSC0_CLKOUT | TIMER4_CLKSEL[3:0] | TIMER4 Functional Clock | |
| DEVICE_CLKOUT_32K | TIMER4_CLKSEL[3:0] | |||
| DEVICE_CLKOUT_32K_CTRL[1:0] | ||||
| MAIN_SYSCLK0/2 | TIMER4_CLKSEL[3:0] | |||
| MAIN_PBIST_CLK | TIMER4_CLKSEL[3:0] | |||
| MAIN_PLL2_HSDIV5_CLKOUT | TIMER4_CLKSEL[3:0] | |||
| CPSW_CLKSEL[2:0] | ||||
| MAIN_PLL0_HSDIV6_CLKOUT | TIMER4_CLKSEL[3:0] | |||
| CPSW_CLKSEL[2:0] | ||||
| CP_GEMAC_CPTS_REF_CLK | TIMER4_CLKSEL[3:0] | |||
| CPSW_CLKSEL[2:0] | ||||
| MCU_EXT_REFCLK0 | TIMER4_CLKSEL[3:0] | |||
| CPSW_CLKSEL[2:0] | ||||
| EXT_REFCLK1 | TIMER4_CLKSEL[3:0] | |||
| CPSW_CLKSEL[2:0] | ||||
| MAIN_PLL4_HSDIV1_CLKOUT | TIMER4_CLKSEL[3:0] | |||
| CPSW_CLKSEL[2:0] | ||||
| MAIN_SYSCLK0 | TIMER4_CLKSEL[3:0] | |||
| CPSW_CLKSEL[2:0] | ||||
| MAIN_PLL2_HSDIV1_CLKOUT/10 | TIMER4_CLKSEL[3:0] | |||
| MAIN_PLL2_HSDIV1_CLKOUT/2 | TIMER4_CLKSEL[3:0] | |||
| MAIN_PBIST_CLK | TIMER4_CLKSEL[3:0] | |||
| MAIN_PLL2_HSDIV1_CLKOUT | TIMER4_CLKSEL[3:0] | |||
| MAIN_PLL2_HSDIV1_CLKOUT/5 | TIMER4_CLKSEL[3:0] | |||
| MAIN_PLL2_HSDIV1_CLKOUT/50 | TIMER4_CLKSEL[3:0] | |||
| MAIN_PLL4_HSDIV2_CLKOUT | TIMER4_CLKSEL[3:0] | |||
| MAIN_PLL0_HSDIV7_CLKOUT | TIMER4_CLKSEL[3:0] | |||
| CLK_12M_RC | TIMER4_CLKSEL[3:0] | |||
| CP_GEMAC_CPTS_REF_CLK | TIMER4_CLKSEL[3:0] | |||
| MAIN_PLL1_HSDIV3_CLKOUT | TIMER4_CLKSEL[3:0] | |||
| MAIN_PLL2_HSDIV6_CLKOUT | TIMER4_CLKSEL[3:0] | |||
| TIMER5 | TIMER_ICLK | MAIN_SYSCLK0/4 | TIMER5 Interface Clock | |
| TIMER_FCLK | HFOSC0_CLKOUT | TIMER5_CTRL[8:8] | TIMER5 Functional Clock | |
| TIMER5_CLKSEL[3:0] | ||||
| DEVICE_CLKOUT_32K | TIMER5_CTRL[8:8] | |||
| TIMER5_CLKSEL[3:0] | ||||
| DEVICE_CLKOUT_32K_CTRL[1:0] | ||||
| MAIN_SYSCLK0/2 | TIMER5_CTRL[8:8] | |||
| TIMER5_CLKSEL[3:0] | ||||
| MAIN_PBIST_CLK | TIMER5_CTRL[8:8] | |||
| TIMER5_CLKSEL[3:0] | ||||
| MAIN_PLL2_HSDIV5_CLKOUT | TIMER5_CTRL[8:8] | |||
| TIMER5_CLKSEL[3:0] | ||||
| CPSW_CLKSEL[2:0] | ||||
| MAIN_PLL0_HSDIV6_CLKOUT | TIMER5_CTRL[8:8] | |||
| TIMER5_CLKSEL[3:0] | ||||
| CPSW_CLKSEL[2:0] | ||||
| CP_GEMAC_CPTS_REF_CLK | TIMER5_CTRL[8:8] | |||
| TIMER5_CLKSEL[3:0] | ||||
| CPSW_CLKSEL[2:0] | ||||
| MCU_EXT_REFCLK0 | TIMER5_CTRL[8:8] | |||
| TIMER5_CLKSEL[3:0] | ||||
| CPSW_CLKSEL[2:0] | ||||
| EXT_REFCLK1 | TIMER5_CTRL[8:8] | |||
| TIMER5_CLKSEL[3:0] | ||||
| CPSW_CLKSEL[2:0] | ||||
| MAIN_PLL4_HSDIV1_CLKOUT | TIMER5_CTRL[8:8] | |||
| TIMER5_CLKSEL[3:0] | ||||
| CPSW_CLKSEL[2:0] | ||||
| MAIN_SYSCLK0 | TIMER5_CTRL[8:8] | |||
| TIMER5_CLKSEL[3:0] | ||||
| CPSW_CLKSEL[2:0] | ||||
| MAIN_PLL2_HSDIV1_CLKOUT/10 | TIMER5_CTRL[8:8] | |||
| TIMER5_CLKSEL[3:0] | ||||
| MAIN_PLL2_HSDIV1_CLKOUT/2 | TIMER5_CTRL[8:8] | |||
| TIMER5_CLKSEL[3:0] | ||||
| MAIN_PLL2_HSDIV1_CLKOUT | TIMER5_CTRL[8:8] | |||
| TIMER5_CLKSEL[3:0] | ||||
| MAIN_PLL2_HSDIV1_CLKOUT/5 | TIMER5_CTRL[8:8] | |||
| TIMER5_CLKSEL[3:0] | ||||
| MAIN_PLL2_HSDIV1_CLKOUT/50 | TIMER5_CTRL[8:8] | |||
| TIMER5_CLKSEL[3:0] | ||||
| MAIN_PLL4_HSDIV2_CLKOUT | TIMER5_CTRL[8:8] | |||
| TIMER5_CLKSEL[3:0] | ||||
| MAIN_PLL0_HSDIV7_CLKOUT | TIMER5_CTRL[8:8] | |||
| TIMER5_CLKSEL[3:0] | ||||
| CLK_12M_RC | TIMER5_CTRL[8:8] | |||
| TIMER5_CLKSEL[3:0] | ||||
| CP_GEMAC_CPTS_REF_CLK | TIMER5_CTRL[8:8] | |||
| TIMER5_CLKSEL[3:0] | ||||
| MAIN_PLL1_HSDIV3_CLKOUT | TIMER5_CTRL[8:8] | |||
| TIMER5_CLKSEL[3:0] | ||||
| MAIN_PLL2_HSDIV6_CLKOUT | TIMER5_CTRL[8:8] | |||
| TIMER5_CLKSEL[3:0] | ||||
| MAIN_SYSCLK0/4 | TIMER5_CTRL[8:8] | |||
| TIMER6 | TIMER_ICLK | MAIN_SYSCLK0/4 | TIMER6 Interface Clock | |
| TIMER_FCLK | HFOSC0_CLKOUT | TIMER6_CLKSEL[3:0] | TIMER6 Functional Clock | |
| DEVICE_CLKOUT_32K | TIMER6_CLKSEL[3:0] | |||
| DEVICE_CLKOUT_32K_CTRL[1:0] | ||||
| MAIN_SYSCLK0/2 | TIMER6_CLKSEL[3:0] | |||
| MAIN_PBIST_CLK | TIMER6_CLKSEL[3:0] | |||
| MAIN_PLL2_HSDIV5_CLKOUT | TIMER6_CLKSEL[3:0] | |||
| CPSW_CLKSEL[2:0] | ||||
| MAIN_PLL0_HSDIV6_CLKOUT | TIMER6_CLKSEL[3:0] | |||
| CPSW_CLKSEL[2:0] | ||||
| CP_GEMAC_CPTS_REF_CLK | TIMER6_CLKSEL[3:0] | |||
| CPSW_CLKSEL[2:0] | ||||
| MCU_EXT_REFCLK0 | TIMER6_CLKSEL[3:0] | |||
| CPSW_CLKSEL[2:0] | ||||
| EXT_REFCLK1 | TIMER6_CLKSEL[3:0] | |||
| CPSW_CLKSEL[2:0] | ||||
| MAIN_PLL4_HSDIV1_CLKOUT | TIMER6_CLKSEL[3:0] | |||
| CPSW_CLKSEL[2:0] | ||||
| MAIN_SYSCLK0 | TIMER6_CLKSEL[3:0] | |||
| CPSW_CLKSEL[2:0] | ||||
| MAIN_PLL2_HSDIV1_CLKOUT/10 | TIMER6_CLKSEL[3:0] | |||
| MAIN_PLL2_HSDIV1_CLKOUT/2 | TIMER6_CLKSEL[3:0] | |||
| MAIN_PLL2_HSDIV1_CLKOUT | TIMER6_CLKSEL[3:0] | |||
| MAIN_PLL2_HSDIV1_CLKOUT/5 | TIMER6_CLKSEL[3:0] | |||
| MAIN_PLL2_HSDIV1_CLKOUT/50 | TIMER6_CLKSEL[3:0] | |||
| MAIN_PLL4_HSDIV2_CLKOUT | TIMER6_CLKSEL[3:0] | |||
| MAIN_PLL0_HSDIV7_CLKOUT | TIMER6_CLKSEL[3:0] | |||
| CLK_12M_RC | TIMER6_CLKSEL[3:0] | |||
| CP_GEMAC_CPTS_REF_CLK | TIMER6_CLKSEL[3:0] | |||
| MAIN_PLL1_HSDIV3_CLKOUT | TIMER6_CLKSEL[3:0] | |||
| MAIN_PLL2_HSDIV6_CLKOUT | TIMER6_CLKSEL[3:0] | |||
| TIMER7 | TIMER_ICLK | MAIN_SYSCLK0/4 | TIMER7 Interface Clock | |
| TIMER_FCLK | HFOSC0_CLKOUT | TIMER7_CTRL[8:8] | TIMER7 Functional Clock | |
| TIMER7_CLKSEL[3:0] | ||||
| DEVICE_CLKOUT_32K | TIMER7_CTRL[8:8] | |||
| TIMER7_CLKSEL[3:0] | ||||
| DEVICE_CLKOUT_32K_CTRL[1:0] | ||||
| MAIN_SYSCLK0/2 | TIMER7_CTRL[8:8] | |||
| TIMER7_CLKSEL[3:0] | ||||
| MAIN_PBIST_CLK | TIMER7_CTRL[8:8] | |||
| TIMER7_CLKSEL[3:0] | ||||
| MAIN_PLL2_HSDIV5_CLKOUT | TIMER7_CTRL[8:8] | |||
| TIMER7_CLKSEL[3:0] | ||||
| CPSW_CLKSEL[2:0] | ||||
| MAIN_PLL0_HSDIV6_CLKOUT | TIMER7_CTRL[8:8] | |||
| TIMER7_CLKSEL[3:0] | ||||
| CPSW_CLKSEL[2:0] | ||||
| CP_GEMAC_CPTS_REF_CLK | TIMER7_CTRL[8:8] | |||
| TIMER7_CLKSEL[3:0] | ||||
| CPSW_CLKSEL[2:0] | ||||
| MCU_EXT_REFCLK0 | TIMER7_CTRL[8:8] | |||
| TIMER7_CLKSEL[3:0] | ||||
| CPSW_CLKSEL[2:0] | ||||
| EXT_REFCLK1 | TIMER7_CTRL[8:8] | |||
| TIMER7_CLKSEL[3:0] | ||||
| CPSW_CLKSEL[2:0] | ||||
| MAIN_PLL4_HSDIV1_CLKOUT | TIMER7_CTRL[8:8] | |||
| TIMER7_CLKSEL[3:0] | ||||
| CPSW_CLKSEL[2:0] | ||||
| MAIN_SYSCLK0 | TIMER7_CTRL[8:8] | |||
| TIMER7_CLKSEL[3:0] | ||||
| CPSW_CLKSEL[2:0] | ||||
| MAIN_PLL2_HSDIV1_CLKOUT/10 | TIMER7_CTRL[8:8] | |||
| TIMER7_CLKSEL[3:0] | ||||
| MAIN_PLL2_HSDIV1_CLKOUT/2 | TIMER7_CTRL[8:8] | |||
| TIMER7_CLKSEL[3:0] | ||||
| MAIN_PLL2_HSDIV1_CLKOUT | TIMER7_CTRL[8:8] | |||
| TIMER7_CLKSEL[3:0] | ||||
| MAIN_PLL2_HSDIV1_CLKOUT/5 | TIMER7_CTRL[8:8] | |||
| TIMER7_CLKSEL[3:0] | ||||
| MAIN_PLL2_HSDIV1_CLKOUT/50 | TIMER7_CTRL[8:8] | |||
| TIMER7_CLKSEL[3:0] | ||||
| MAIN_PLL4_HSDIV2_CLKOUT | TIMER7_CTRL[8:8] | |||
| TIMER7_CLKSEL[3:0] | ||||
| MAIN_PLL0_HSDIV7_CLKOUT | TIMER7_CTRL[8:8] | |||
| TIMER7_CLKSEL[3:0] | ||||
| CLK_12M_RC | TIMER7_CTRL[8:8] | |||
| TIMER7_CLKSEL[3:0] | ||||
| MAIN_PLL1_HSDIV3_CLKOUT | TIMER7_CTRL[8:8] | |||
| TIMER7_CLKSEL[3:0] | ||||
| MAIN_PLL2_HSDIV6_CLKOUT | TIMER7_CTRL[8:8] | |||
| TIMER7_CLKSEL[3:0] | ||||
| MAIN_PBIST_CLK | TIMER7_CTRL[8:8] | |||
| MAIN_SYSCLK0/4 | TIMER7_CTRL[8:8] | |||
| TIMER8 | TIMER_ICLK | MAIN_SYSCLK0/4 | TIMER8 Interface Clock | |
| TIMER_FCLK | HFOSC0_CLKOUT | TIMER8_CLKSEL[3:0] | TIMER8 Functional Clock | |
| DEVICE_CLKOUT_32K | TIMER8_CLKSEL[3:0] | |||
| DEVICE_CLKOUT_32K_CTRL[1:0] | ||||
| MAIN_SYSCLK0/2 | TIMER8_CLKSEL[3:0] | |||
| MAIN_PBIST_CLK | TIMER8_CLKSEL[3:0] | |||
| MAIN_PLL2_HSDIV5_CLKOUT | TIMER8_CLKSEL[3:0] | |||
| CPSW_CLKSEL[2:0] | ||||
| MAIN_PLL0_HSDIV6_CLKOUT | TIMER8_CLKSEL[3:0] | |||
| CPSW_CLKSEL[2:0] | ||||
| CP_GEMAC_CPTS_REF_CLK | TIMER8_CLKSEL[3:0] | |||
| CPSW_CLKSEL[2:0] | ||||
| MCU_EXT_REFCLK0 | TIMER8_CLKSEL[3:0] | |||
| CPSW_CLKSEL[2:0] | ||||
| EXT_REFCLK1 | TIMER8_CLKSEL[3:0] | |||
| CPSW_CLKSEL[2:0] | ||||
| MAIN_PLL4_HSDIV1_CLKOUT | TIMER8_CLKSEL[3:0] | |||
| CPSW_CLKSEL[2:0] | ||||
| MAIN_SYSCLK0 | TIMER8_CLKSEL[3:0] | |||
| CPSW_CLKSEL[2:0] | ||||
| MAIN_PLL2_HSDIV1_CLKOUT/10 | TIMER8_CLKSEL[3:0] | |||
| MAIN_PLL2_HSDIV1_CLKOUT/2 | TIMER8_CLKSEL[3:0] | |||
| MAIN_PLL2_HSDIV1_CLKOUT | TIMER8_CLKSEL[3:0] | |||
| MAIN_PBIST_CLK | TIMER8_CLKSEL[3:0] | |||
| MAIN_PLL2_HSDIV1_CLKOUT/50 | TIMER8_CLKSEL[3:0] | |||
| MAIN_PLL4_HSDIV2_CLKOUT | TIMER8_CLKSEL[3:0] | |||
| MAIN_PLL0_HSDIV7_CLKOUT | TIMER8_CLKSEL[3:0] | |||
| CLK_12M_RC | TIMER8_CLKSEL[3:0] | |||
| MCU_EXT_REFCLK0 | TIMER8_CLKSEL[3:0] | |||
| EXT_REFCLK1 | TIMER8_CLKSEL[3:0] | |||
| MCU_TIEOFF0 | TIMER8_CLKSEL[3:0] | |||
| MAIN_PLL1_HSDIV3_CLKOUT | TIMER8_CLKSEL[3:0] | |||
| MAIN_PLL2_HSDIV6_CLKOUT | TIMER8_CLKSEL[3:0] | |||
| TIMER9 | TIMER_ICLK | MAIN_SYSCLK0/4 | TIMER9 Interface Clock | |
| TIMER_FCLK | HFOSC0_CLKOUT | TIMER9_CTRL[8:8] | TIMER9 Functional Clock | |
| TIMER9_CLKSEL[3:0] | ||||
| DEVICE_CLKOUT_32K | TIMER9_CTRL[8:8] | |||
| TIMER9_CLKSEL[3:0] | ||||
| DEVICE_CLKOUT_32K_CTRL[1:0] | ||||
| MAIN_SYSCLK0/2 | TIMER9_CTRL[8:8] | |||
| TIMER9_CLKSEL[3:0] | ||||
| MAIN_PBIST_CLK | TIMER9_CTRL[8:8] | |||
| TIMER9_CLKSEL[3:0] | ||||
| MAIN_PLL2_HSDIV5_CLKOUT | TIMER9_CTRL[8:8] | |||
| TIMER9_CLKSEL[3:0] | ||||
| CPSW_CLKSEL[2:0] | ||||
| MAIN_PLL0_HSDIV6_CLKOUT | TIMER9_CTRL[8:8] | |||
| TIMER9_CLKSEL[3:0] | ||||
| CPSW_CLKSEL[2:0] | ||||
| CP_GEMAC_CPTS_REF_CLK | TIMER9_CTRL[8:8] | |||
| TIMER9_CLKSEL[3:0] | ||||
| CPSW_CLKSEL[2:0] | ||||
| MCU_EXT_REFCLK0 | TIMER9_CTRL[8:8] | |||
| TIMER9_CLKSEL[3:0] | ||||
| CPSW_CLKSEL[2:0] | ||||
| EXT_REFCLK1 | TIMER9_CTRL[8:8] | |||
| TIMER9_CLKSEL[3:0] | ||||
| CPSW_CLKSEL[2:0] | ||||
| MAIN_PLL4_HSDIV1_CLKOUT | TIMER9_CTRL[8:8] | |||
| TIMER9_CLKSEL[3:0] | ||||
| CPSW_CLKSEL[2:0] | ||||
| MAIN_SYSCLK0 | TIMER9_CTRL[8:8] | |||
| TIMER9_CLKSEL[3:0] | ||||
| CPSW_CLKSEL[2:0] | ||||
| MAIN_PLL2_HSDIV1_CLKOUT/10 | TIMER9_CTRL[8:8] | |||
| TIMER9_CLKSEL[3:0] | ||||
| MAIN_PLL2_HSDIV1_CLKOUT/2 | TIMER9_CTRL[8:8] | |||
| TIMER9_CLKSEL[3:0] | ||||
| MAIN_PLL2_HSDIV1_CLKOUT | TIMER9_CTRL[8:8] | |||
| TIMER9_CLKSEL[3:0] | ||||
| MAIN_PLL2_HSDIV1_CLKOUT/5 | TIMER9_CTRL[8:8] | |||
| TIMER9_CLKSEL[3:0] | ||||
| MAIN_PLL2_HSDIV1_CLKOUT/50 | TIMER9_CTRL[8:8] | |||
| TIMER9_CLKSEL[3:0] | ||||
| MAIN_PLL4_HSDIV2_CLKOUT | TIMER9_CTRL[8:8] | |||
| TIMER9_CLKSEL[3:0] | ||||
| MAIN_PLL0_HSDIV7_CLKOUT | TIMER9_CTRL[8:8] | |||
| TIMER9_CLKSEL[3:0] | ||||
| CLK_12M_RC | TIMER9_CTRL[8:8] | |||
| TIMER9_CLKSEL[3:0] | ||||
| MAIN_PLL1_HSDIV3_CLKOUT | TIMER9_CTRL[8:8] | |||
| TIMER9_CLKSEL[3:0] | ||||
| MAIN_PLL2_HSDIV6_CLKOUT | TIMER9_CTRL[8:8] | |||
| TIMER9_CLKSEL[3:0] | ||||
| MAIN_PBIST_CLK | TIMER9_CTRL[8:8] | |||
| MAIN_SYSCLK0/4 | TIMER9_CTRL[8:8] | |||
| TIMER10 | TIMER_ICLK | MAIN_SYSCLK0/4 | TIMER10 Interface Clock | |
| TIMER_FCLK | HFOSC0_CLKOUT | TIMER10_CLKSEL[3:0] | TIMER10 Functional Clock | |
| DEVICE_CLKOUT_32K | TIMER10_CLKSEL[3:0] | |||
| DEVICE_CLKOUT_32K_CTRL[1:0] | ||||
| MAIN_SYSCLK0/2 | TIMER10_CLKSEL[3:0] | |||
| MAIN_PBIST_CLK | TIMER10_CLKSEL[3:0] | |||
| MAIN_PLL2_HSDIV5_CLKOUT | TIMER10_CLKSEL[3:0] | |||
| CPSW_CLKSEL[2:0] | ||||
| MAIN_PLL0_HSDIV6_CLKOUT | TIMER10_CLKSEL[3:0] | |||
| CPSW_CLKSEL[2:0] | ||||
| CP_GEMAC_CPTS_REF_CLK | TIMER10_CLKSEL[3:0] | |||
| CPSW_CLKSEL[2:0] | ||||
| MCU_EXT_REFCLK0 | TIMER10_CLKSEL[3:0] | |||
| CPSW_CLKSEL[2:0] | ||||
| EXT_REFCLK1 | TIMER10_CLKSEL[3:0] | |||
| CPSW_CLKSEL[2:0] | ||||
| MAIN_PLL4_HSDIV1_CLKOUT | TIMER10_CLKSEL[3:0] | |||
| CPSW_CLKSEL[2:0] | ||||
| MAIN_SYSCLK0 | TIMER10_CLKSEL[3:0] | |||
| CPSW_CLKSEL[2:0] | ||||
| MAIN_PLL2_HSDIV1_CLKOUT/10 | TIMER10_CLKSEL[3:0] | |||
| MAIN_PLL2_HSDIV1_CLKOUT/2 | TIMER10_CLKSEL[3:0] | |||
| MAIN_PLL2_HSDIV1_CLKOUT | TIMER10_CLKSEL[3:0] | |||
| MAIN_PLL2_HSDIV1_CLKOUT/5 | TIMER10_CLKSEL[3:0] | |||
| MAIN_PLL2_HSDIV1_CLKOUT/50 | TIMER10_CLKSEL[3:0] | |||
| MAIN_PLL4_HSDIV2_CLKOUT | TIMER10_CLKSEL[3:0] | |||
| MAIN_PLL0_HSDIV7_CLKOUT | TIMER10_CLKSEL[3:0] | |||
| CLK_12M_RC | TIMER10_CLKSEL[3:0] | |||
| MCU_EXT_REFCLK0 | TIMER10_CLKSEL[3:0] | |||
| MAIN_PLL1_HSDIV3_CLKOUT | TIMER10_CLKSEL[3:0] | |||
| MAIN_PLL2_HSDIV6_CLKOUT | TIMER10_CLKSEL[3:0] | |||
| TIMER11 | TIMER_ICLK | MAIN_SYSCLK0/4 | TIMER11 Interface Clock | |
| TIMER_FCLK | HFOSC0_CLKOUT | TIMER11_CTRL[8:8] | TIMER11 Functional Clock | |
| TIMER11_CLKSEL[3:0] | ||||
| DEVICE_CLKOUT_32K | TIMER11_CTRL[8:8] | |||
| TIMER11_CLKSEL[3:0] | ||||
| ] | ||||
| MAIN_SYSCLK0/2 | TIMER11_CTRL[8:8] | |||
| TIMER11_CLKSEL[3:0] | ||||
| MAIN_PBIST_CLK | TIMER11_CTRL[8:8] | |||
| TIMER11_CLKSEL[3:0] | ||||
| MAIN_PLL2_HSDIV5_CLKOUT | TIMER11_CTRL[8:8] | |||
| TIMER11_CLKSEL[3:0] | ||||
| CPSW_CLKSEL[2:0] | ||||
| MAIN_PLL0_HSDIV6_CLKOUT | TIMER11_CTRL[8:8] | |||
| TIMER11_CLKSEL[3:0] | ||||
| CPSW_CLKSEL[2:0] | ||||
| CP_GEMAC_CPTS_REF_CLK | TIMER11_CTRL[8:8] | |||
| TIMER11_CLKSEL[3:0] | ||||
| CPSW_CLKSEL[2:0] | ||||
| MCU_EXT_REFCLK0 | TIMER11_CTRL[8:8] | |||
| TIMER11_CLKSEL[3:0] | ||||
| CPSW_CLKSEL[2:0] | ||||
| EXT_REFCLK1 | TIMER11_CTRL[8:8] | |||
| TIMER11_CLKSEL[3:0] | ||||
| CPSW_CLKSEL[2:0] | ||||
| MAIN_PLL4_HSDIV1_CLKOUT | TIMER11_CTRL[8:8] | |||
| TIMER11_CLKSEL[3:0] | ||||
| CPSW_CLKSEL[2:0] | ||||
| MAIN_SYSCLK0 | TIMER11_CTRL[8:8] | |||
| TIMER11_CLKSEL[3:0] | ||||
| CPSW_CLKSEL[2:0] | ||||
| MAIN_PLL2_HSDIV1_CLKOUT/10 | TIMER11_CTRL[8:8] | |||
| TIMER11_CLKSEL[3:0] | ||||
| MAIN_PLL2_HSDIV1_CLKOUT/2 | TIMER11_CTRL[8:8] | |||
| TIMER11_CLKSEL[3:0] | ||||
| MAIN_PLL2_HSDIV1_CLKOUT | TIMER11_CTRL[8:8] | |||
| TIMER11_CLKSEL[3:0] | ||||
| MAIN_PLL2_HSDIV1_CLKOUT/5 | TIMER11_CTRL[8:8] | |||
| TIMER11_CLKSEL[3:0] | ||||
| MAIN_PLL2_HSDIV1_CLKOUT/50 | TIMER11_CTRL[8:8] | |||
| TIMER11_CLKSEL[3:0] | ||||
| MAIN_PLL4_HSDIV2_CLKOUT | TIMER11_CTRL[8:8] | |||
| TIMER11_CLKSEL[3:0] | ||||
| MAIN_PLL0_HSDIV7_CLKOUT | TIMER11_CTRL[8:8] | |||
| TIMER11_CLKSEL[3:0] | ||||
| CLK_12M_RC | TIMER11_CTRL[8:8] | |||
| TIMER11_CLKSEL[3:0] | ||||
| MAIN_PLL1_HSDIV3_CLKOUT | TIMER11_CTRL[8:8] | |||
| TIMER11_CLKSEL[3:0] | ||||
| MAIN_PLL2_HSDIV6_CLKOUT | TIMER11_CTRL[8:8] | |||
| TIMER11_CLKSEL[3:0] | ||||
| MAIN_SYSCLK0/4 | TIMER11_CTRL[8:8] | |||
| TIMER12 | TIMER_ICLK | MAIN_SYSCLK0/4 | TIMER12 Interface Clock | |
| TIMER_FCLK | HFOSC0_CLKOUT | TIMER12_CLKSEL[3:0] | TIMER12 Functional Clock | |
| DEVICE_CLKOUT_32K | TIMER12_CLKSEL[3:0] | |||
| DEVICE_CLKOUT_32K_CTRL[1:0] | ||||
| MAIN_SYSCLK0/2 | TIMER12_CLKSEL[3:0] | |||
| MAIN_PBIST_CLK | TIMER12_CLKSEL[3:0] | |||
| MAIN_PLL2_HSDIV5_CLKOUT | TIMER12_CLKSEL[3:0] | |||
| CPSW_CLKSEL[2:0] | ||||
| MAIN_PLL0_HSDIV6_CLKOUT | TIMER12_CLKSEL[3:0] | |||
| CPSW_CLKSEL[2:0] | ||||
| CP_GEMAC_CPTS_REF_CLK | TIMER12_CLKSEL[3:0] | |||
| CPSW_CLKSEL[2:0] | ||||
| MCU_EXT_REFCLK0 | TIMER12_CLKSEL[3:0] | |||
| CPSW_CLKSEL[2:0] | ||||
| EXT_REFCLK1 | TIMER12_CLKSEL[3:0] | |||
| CPSW_CLKSEL[2:0] | ||||
| MAIN_PLL4_HSDIV1_CLKOUT | TIMER12_CLKSEL[3:0] | |||
| CPSW_CLKSEL[2:0] | ||||
| MAIN_SYSCLK0 | TIMER12_CLKSEL[3:0] | |||
| CPSW_CLKSEL[2:0] | ||||
| MAIN_PLL2_HSDIV1_CLKOUT/10 | TIMER12_CLKSEL[3:0] | |||
| MAIN_PLL2_HSDIV1_CLKOUT/2 | TIMER12_CLKSEL[3:0] | |||
| MAIN_PLL2_HSDIV1_CLKOUT | TIMER12_CLKSEL[3:0] | |||
| MAIN_PLL2_HSDIV1_CLKOUT/5 | TIMER12_CLKSEL[3:0] | |||
| MAIN_PLL2_HSDIV1_CLKOUT/50 | TIMER12_CLKSEL[3:0] | |||
| MAIN_PLL4_HSDIV2_CLKOUT | TIMER12_CLKSEL[3:0] | |||
| MAIN_PLL0_HSDIV7_CLKOUT | TIMER12_CLKSEL[3:0] | |||
| CLK_12M_RC | TIMER12_CLKSEL[3:0] | |||
| MAIN_PLL1_HSDIV3_CLKOUT | TIMER12_CLKSEL[3:0] | |||
| MAIN_PLL2_HSDIV6_CLKOUT | TIMER12_CLKSEL[3:0] | |||
| TIMER13 | TIMER_ICLK | MAIN_SYSCLK0/4 | TIMER13 Interface Clock | |
| TIMER_FCLK | HFOSC0_CLKOUT | TIMER13_CTRL[8:8] | TIMER13 Functional Clock | |
| TIMER13_CLKSEL[3:0] | ||||
| DEVICE_CLKOUT_32K | TIMER13_CTRL[8:8] | |||
| TIMER13_CLKSEL[3:0] | ||||
| DEVICE_CLKOUT_32K_CTRL[1:0] | ||||
| MAIN_SYSCLK0/2 | TIMER13_CTRL[8:8] | |||
| TIMER13_CLKSEL[3:0] | ||||
| MAIN_PBIST_CLK | TIMER13_CTRL[8:8] | |||
| TIMER13_CLKSEL[3:0] | ||||
| MAIN_PLL2_HSDIV5_CLKOUT | TIMER13_CTRL[8:8] | |||
| TIMER13_CLKSEL[3:0] | ||||
| CPSW_CLKSEL[2:0] | ||||
| MAIN_PLL0_HSDIV6_CLKOUT | TIMER13_CTRL[8:8] | |||
| TIMER13_CLKSEL[3:0] | ||||
| CPSW_CLKSEL[2:0] | ||||
| CP_GEMAC_CPTS_REF_CLK | TIMER13_CTRL[8:8] | |||
| TIMER13_CLKSEL[3:0] | ||||
| CPSW_CLKSEL[2:0] | ||||
| MCU_EXT_REFCLK0 | TIMER13_CTRL[8:8] | |||
| TIMER13_CLKSEL[3:0] | ||||
| CPSW_CLKSEL[2:0] | ||||
| EXT_REFCLK1 | TIMER13_CTRL[8:8] | |||
| TIMER13_CLKSEL[3:0] | ||||
| CPSW_CLKSEL[2:0] | ||||
| MAIN_PLL4_HSDIV1_CLKOUT | TIMER13_CTRL[8:8] | |||
| TIMER13_CLKSEL[3:0] | ||||
| CPSW_CLKSEL[2:0] | ||||
| MAIN_SYSCLK0 | TIMER13_CTRL[8:8] | |||
| TIMER13_CLKSEL[3:0] | ||||
| CPSW_CLKSEL[2:0] | ||||
| MAIN_PLL2_HSDIV1_CLKOUT/10 | TIMER13_CTRL[8:8] | |||
| TIMER13_CLKSEL[3:0] | ||||
| MAIN_PLL2_HSDIV1_CLKOUT/2 | TIMER13_CTRL[8:8] | |||
| TIMER13_CLKSEL[3:0] | ||||
| MAIN_PLL2_HSDIV1_CLKOUT | TIMER13_CTRL[8:8] | |||
| TIMER13_CLKSEL[3:0] | ||||
| MAIN_PLL2_HSDIV1_CLKOUT/5 | TIMER13_CTRL[8:8] | |||
| TIMER13_CLKSEL[3:0] | ||||
| MAIN_PLL2_HSDIV1_CLKOUT/50 | TIMER13_CTRL[8:8] | |||
| TIMER13_CLKSEL[3:0] | ||||
| MAIN_PLL4_HSDIV2_CLKOUT | TIMER13_CTRL[8:8] | |||
| TIMER13_CLKSEL[3:0] | ||||
| MAIN_PLL0_HSDIV7_CLKOUT | TIMER13_CTRL[8:8] | |||
| TIMER13_CLKSEL[3:0] | ||||
| CLK_12M_RC | TIMER13_CTRL[8:8] | |||
| TIMER13_CLKSEL[3:0] | ||||
| MAIN_PLL1_HSDIV3_CLKOUT | TIMER13_CTRL[8:8] | |||
| TIMER13_CLKSEL[3:0] | ||||
| MAIN_PLL2_HSDIV6_CLKOUT | TIMER13_CTRL[8:8] | |||
| TIMER13_CLKSEL[3:0] | ||||
| MAIN_SYSCLK0/4 | TIMER13_CTRL[8:8] | |||
| TIMER14 | TIMER_ICLK | MAIN_SYSCLK0/4 | TIMER14 Interface Clock | |
| TIMER_FCLK | HFOSC0_CLKOUT | TIMER14_CLKSEL[3:0] | TIMER14 Functional Clock | |
| DEVICE_CLKOUT_32K | TIMER14_CLKSEL[3:0] | |||
| DEVICE_CLKOUT_32K_CTRL[1:0] | ||||
| MAIN_SYSCLK0/2 | TIMER14_CLKSEL[3:0] | |||
| MAIN_PBIST_CLK | TIMER14_CLKSEL[3:0] | |||
| MAIN_PLL2_HSDIV5_CLKOUT | TIMER14_CLKSEL[3:0] | |||
| CPSW_CLKSEL[2:0] | ||||
| MAIN_PLL0_HSDIV6_CLKOUT | TIMER14_CLKSEL[3:0] | |||
| CPSW_CLKSEL[2:0] | ||||
| CP_GEMAC_CPTS_REF_CLK | TIMER14_CLKSEL[3:0] | |||
| CPSW_CLKSEL[2:0] | ||||
| MCU_EXT_REFCLK0 | TIMER14_CLKSEL[3:0] | |||
| CPSW_CLKSEL[2:0] | ||||
| EXT_REFCLK1 | TIMER14_CLKSEL[3:0] | |||
| CPSW_CLKSEL[2:0] | ||||
| MAIN_PLL4_HSDIV1_CLKOUT | TIMER14_CLKSEL[3:0] | |||
| CPSW_CLKSEL[2:0] | ||||
| MAIN_SYSCLK0 | TIMER14_CLKSEL[3:0] | |||
| CPSW_CLKSEL[2:0] | ||||
| MAIN_PLL2_HSDIV1_CLKOUT/10 | TIMER14_CLKSEL[3:0] | |||
| MAIN_PLL2_HSDIV1_CLKOUT/2 | TIMER14_CLKSEL[3:0] | |||
| MAIN_PLL2_HSDIV1_CLKOUT | TIMER14_CLKSEL[3:0] | |||
| MAIN_PLL2_HSDIV1_CLKOUT/5 | TIMER14_CLKSEL[3:0] | |||
| MAIN_PLL2_HSDIV1_CLKOUT/50 | TIMER14_CLKSEL[3:0] | |||
| MAIN_PLL4_HSDIV2_CLKOUT | TIMER14_CLKSEL[3:0] | |||
| MAIN_PLL0_HSDIV7_CLKOUT | TIMER14_CLKSEL[3:0] | |||
| CLK_12M_RC | TIMER14_CLKSEL[3:0] | |||
| MAIN_PLL1_HSDIV3_CLKOUT | TIMER14_CLKSEL[3:0] | |||
| MAIN_PLL2_HSDIV6_CLKOUT | TIMER14_CLKSEL[3:0] | |||
| TIMER15 | TIMER_ICLK | MAIN_SYSCLK0/4 | TIMER15 Interface Clock | |
| TIMER_FCLK | HFOSC0_CLKOUT | TIMER15_CTRL[8:8] | TIMER15 Functional Clock | |
| TIMER15_CLKSEL[3:0] | ||||
| DEVICE_CLKOUT_32K | TIMER15_CTRL[8:8] | |||
| TIMER15_CLKSEL[3:0] | ||||
| DEVICE_CLKOUT_32K_CTRL[1:0] | ||||
| MAIN_SYSCLK0/2 | TIMER15_CTRL[8:8] | |||
| TIMER15_CLKSEL[3:0] | ||||
| MAIN_PBIST_CLK | TIMER15_CTRL[8:8] | |||
| TIMER15_CLKSEL[3:0] | ||||
| MAIN_PLL2_HSDIV5_CLKOUT | TIMER15_CTRL[8:8] | |||
| TIMER15_CLKSEL[3:0] | ||||
| CPSW_CLKSEL[2:0] | ||||
| MAIN_PLL0_HSDIV6_CLKOUT | TIMER15_CTRL[8:8] | |||
| TIMER15_CLKSEL[3:0] | ||||
| CPSW_CLKSEL[2:0] | ||||
| CP_GEMAC_CPTS_REF_CLK | TIMER15_CTRL[8:8] | |||
| TIMER15_CLKSEL[3:0] | ||||
| CPSW_CLKSEL[2:0] | ||||
| MCU_EXT_REFCLK0 | TIMER15_CTRL[8:8] | |||
| TIMER15_CLKSEL[3:0] | ||||
| CPSW_CLKSEL[2:0] | ||||
| EXT_REFCLK1 | TIMER15_CTRL[8:8] | |||
| TIMER15_CLKSEL[3:0] | ||||
| CPSW_CLKSEL[2:0] | ||||
| MAIN_PLL4_HSDIV1_CLKOUT | TIMER15_CTRL[8:8] | |||
| TIMER15_CLKSEL[3:0] | ||||
| CPSW_CLKSEL[2:0] | ||||
| MAIN_SYSCLK0 | TIMER15_CTRL[8:8] | |||
| TIMER15_CLKSEL[3:0] | ||||
| CPSW_CLKSEL[2:0] | ||||
| MAIN_PLL2_HSDIV1_CLKOUT/10 | TIMER15_CTRL[8:8] | |||
| TIMER15_CLKSEL[3:0] | ||||
| MAIN_PLL2_HSDIV1_CLKOUT/2 | TIMER15_CTRL[8:8] | |||
| TIMER15_CLKSEL[3:0] | ||||
| MAIN_PLL2_HSDIV1_CLKOUT | TIMER15_CTRL[8:8] | |||
| TIMER15_CLKSEL[3:0] | ||||
| MAIN_PLL2_HSDIV1_CLKOUT/5 | TIMER15_CTRL[8:8] | |||
| TIMER15_CLKSEL[3:0] | ||||
| MAIN_PLL2_HSDIV1_CLKOUT/50 | TIMER15_CTRL[8:8] | |||
| TIMER15_CLKSEL[3:0] | ||||
| MAIN_PLL4_HSDIV2_CLKOUT | TIMER15_CTRL[8:8] | |||
| TIMER15_CLKSEL[3:0] | ||||
| MAIN_PLL0_HSDIV7_CLKOUT | TIMER15_CTRL[8:8] | |||
| TIMER15_CLKSEL[3:0] | ||||
| CLK_12M_RC | TIMER15_CTRL[8:8] | |||
| TIMER15_CLKSEL[3:0] | ||||
| CP_GEMAC_CPTS_REF_CLK | TIMER15_CTRL[8:8] | |||
| TIMER15_CLKSEL[3:0] | ||||
| MAIN_PLL1_HSDIV3_CLKOUT | TIMER15_CTRL[8:8] | |||
| TIMER15_CLKSEL[3:0] | ||||
| MAIN_PLL2_HSDIV6_CLKOUT | TIMER15_CTRL[8:8] | |||
| TIMER15_CLKSEL[3:0] | ||||
| MAIN_PBIST_CLK | TIMER15_CTRL[8:8] | |||
| MAIN_SYSCLK0/4 | TIMER15_CTRL[8:8] | |||
| WKUP_TIMER0 | TIMER_ICLK | DM_CLK/2 | WKUP_CLKSEL[0:0] | WKUP_TIMER0 Interface Clock |
| TIMER_FCLK | HFOSC0_CLKOUT | WKUP_TIMER0_CLKSEL[2:0] | WKUP_TIMER0 Functional Clock | |
| DM_CLK/2 | WKUP_TIMER0_CLKSEL[2:0] | |||
| WKUP_CLKSEL[0:0] | ||||
| CLK_12M_RC | WKUP_TIMER0_CLKSEL[2:0] | |||
| MCU_PLL0_HSDIV5_CLKOUT | WKUP_TIMER0_CLKSEL[2:0] | |||
| DEVICE_CLKOUT_32K | WKUP_TIMER0_CLKSEL[2:0] | |||
| DEVICE_CLKOUT_32K_CTRL[1:0] | ||||
| MAIN_SYSCLK0/2 | WKUP_TIMER0_CLKSEL[2:0] | |||
| MAIN_PBIST_CLK | WKUP_TIMER0_CLKSEL[2:0] | |||
| MAIN_PLL2_HSDIV5_CLKOUT | WKUP_TIMER0_CLKSEL[2:0] | |||
| CPSW_CLKSEL[2:0] | ||||
| MAIN_PLL0_HSDIV6_CLKOUT | WKUP_TIMER0_CLKSEL[2:0] | |||
| CPSW_CLKSEL[2:0] | ||||
| CP_GEMAC_CPTS_REF_CLK | WKUP_TIMER0_CLKSEL[2:0] | |||
| CPSW_CLKSEL[2:0] | ||||
| MCU_EXT_REFCLK0 | WKUP_TIMER0_CLKSEL[2:0] | |||
| CPSW_CLKSEL[2:0] | ||||
| EXT_REFCLK1 | WKUP_TIMER0_CLKSEL[2:0] | |||
| CPSW_CLKSEL[2:0] | ||||
| MAIN_PLL4_HSDIV1_CLKOUT | WKUP_TIMER0_CLKSEL[2:0] | |||
| CPSW_CLKSEL[2:0] | ||||
| MAIN_SYSCLK0 | WKUP_TIMER0_CLKSEL[2:0] | |||
| CPSW_CLKSEL[2:0] | ||||
| MAIN_PLL2_HSDIV1_CLKOUT/10 | WKUP_TIMER0_CLKSEL[2:0] | |||
| MAIN_PLL2_HSDIV1_CLKOUT/2 | WKUP_TIMER0_CLKSEL[2:0] | |||
| MAIN_PLL2_HSDIV1_CLKOUT | WKUP_TIMER0_CLKSEL[2:0] | |||
| MAIN_PLL2_HSDIV1_CLKOUT/5 | WKUP_TIMER0_CLKSEL[2:0] | |||
| MAIN_PLL2_HSDIV1_CLKOUT/50 | WKUP_TIMER0_CLKSEL[2:0] | |||
| CLK_32K_RC | WKUP_TIMER0_CLKSEL[2:0] | |||
| WKUP_TIMER1 | TIMER_ICLK | DM_CLK/2 | WKUP_CLKSEL[0:0] | WKUP_TIMER1 Interface Clock |
| TIMER_FCLK | HFOSC0_CLKOUT | WKUP_TIMER1_CTRL[8:8] | WKUP_TIMER1 Functional Clock | |
| WKUP_TIMER1_CLKSEL[2:0] | ||||
| DM_CLK/2 | WKUP_TIMER1_CTRL[8:8] | |||
| WKUP_TIMER1_CLKSEL[2:0] | ||||
| WKUP_CLKSEL[0:0] | ||||
| CLK_12M_RC | WKUP_TIMER1_CTRL[8:8] | |||
| WKUP_TIMER1_CLKSEL[2:0] | ||||
| MCU_PLL0_HSDIV5_CLKOUT | WKUP_TIMER1_CTRL[8:8] | |||
| WKUP_TIMER1_CLKSEL[2:0] | ||||
| MCU_EXT_REFCLK0 | WKUP_TIMER1_CTRL[8:8] | |||
| WKUP_TIMER1_CLKSEL[2:0] | ||||
| DEVICE_CLKOUT_32K | WKUP_TIMER1_CTRL[8:8] | |||
| WKUP_TIMER1_CLKSEL[2:0] | ||||
| DEVICE_CLKOUT_32K_CTRL[1:0] | ||||
| MAIN_SYSCLK0/2 | WKUP_TIMER1_CTRL[8:8] | |||
| WKUP_TIMER1_CLKSEL[2:0] | ||||
| MAIN_PBIST_CLK | WKUP_TIMER1_CTRL[8:8] | |||
| WKUP_TIMER1_CLKSEL[2:0] | ||||
| MAIN_PLL2_HSDIV5_CLKOUT | WKUP_TIMER1_CTRL[8:8] | |||
| WKUP_TIMER1_CLKSEL[2:0] | ||||
| CPSW_CLKSEL[2:0] | ||||
| MAIN_PLL0_HSDIV6_CLKOUT | WKUP_TIMER1_CTRL[8:8] | |||
| WKUP_TIMER1_CLKSEL[2:0] | ||||
| CPSW_CLKSEL[2:0] | ||||
| CP_GEMAC_CPTS_REF_CLK | WKUP_TIMER1_CTRL[8:8] | |||
| WKUP_TIMER1_CLKSEL[2:0] | ||||
| CPSW_CLKSEL[2:0] | ||||
| MCU_EXT_REFCLK0 | WKUP_TIMER1_CTRL[8:8] | |||
| WKUP_TIMER1_CLKSEL[2:0] | ||||
| CPSW_CLKSEL[2:0] | ||||
| EXT_REFCLK1 | WKUP_TIMER1_CTRL[8:8] | |||
| WKUP_TIMER1_CLKSEL[2:0] | ||||
| CPSW_CLKSEL[2:0] | ||||
| MAIN_PLL4_HSDIV1_CLKOUT | WKUP_TIMER1_CTRL[8:8] | |||
| WKUP_TIMER1_CLKSEL[2:0] | ||||
| CPSW_CLKSEL[2:0] | ||||
| MAIN_SYSCLK0 | WKUP_TIMER1_CTRL[8:8] | |||
| WKUP_TIMER1_CLKSEL[2:0] | ||||
| CPSW_CLKSEL[2:0] | ||||
| MAIN_PLL2_HSDIV1_CLKOUT/10 | WKUP_TIMER1_CTRL[8:8] | |||
| WKUP_TIMER1_CLKSEL[2:0] | ||||
| MAIN_PLL2_HSDIV1_CLKOUT/2 | WKUP_TIMER1_CTRL[8:8] | |||
| WKUP_TIMER1_CLKSEL[2:0] | ||||
| MAIN_PLL2_HSDIV1_CLKOUT | WKUP_TIMER1_CTRL[8:8] | |||
| WKUP_TIMER1_CLKSEL[2:0] | ||||
| MAIN_PLL2_HSDIV1_CLKOUT/5 | WKUP_TIMER1_CTRL[8:8] | |||
| WKUP_TIMER1_CLKSEL[2:0] | ||||
| MAIN_PLL2_HSDIV1_CLKOUT/50 | WKUP_TIMER1_CTRL[8:8] | |||
| WKUP_TIMER1_CLKSEL[2:0] | ||||
| CLK_32K_RC | WKUP_TIMER1_CTRL[8:8] | |||
| WKUP_TIMER1_CLKSEL[2:0] | ||||
| DM_CLK/2 | WKUP_TIMER1_CTRL[8:8] | |||
| WKUP_CLKSEL[0:0] | ||||