SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register contains bits for indicating overcurrent condition on VBUS to Controller
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| Instance Name | Physical Address |
|---|---|
| USB0 | 0F90 0004h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RSVD3 | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RSVD3 | OVERCURRENT_N | ||||||
| R | R/W | ||||||
| 0h | 1h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RSVD2 | OVERCURRENT_SEL | ||||||
| R | R/W | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RSVD1 | |||||||
| R | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:17 | RSVD3 | R | 0h | Reserved bits Reset Source: cfg_srst_n |
| 16 | OVERCURRENT_N | R/W | 1h | Overcurrent indicator to the Controller Reset Source: cfg_srst_n |
| 15:9 | RSVD2 | R | 0h | Reserved bits Reset Source: cfg_srst_n |
| 8 | OVERCURRENT_SEL | R/W | 0h | Overcurrent MMR select. Has to be written before setting pwrup_rst_n bit. 1 - overcurrent MMR bit is used, 0 - port_overcurrent_n input is used Reset Source: cfg_srst_n |
| 7:0 | RSVD1 | R | 0h | Reserved bits Reset Source: cfg_srst_n |