SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The Interrupt Masked Status Register holds the masked status for the FLC/RL2 status/error interrupts. Writing to this register will EOI the interrupt, that is if another interrupt is pending, a new pulse interrupt will be generated.
Return to Summary Table
| Instance Name | Physical Address |
|---|---|
| RL2_0 | 2500 0084h |
| RL2_0 | 2500 1084h |
| RL2_2 | 2500 2084h |
| RL2_3 | 2500 3084h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | FLC_DON | FLC_WRERR | FLC_RDERR | WR_HIT | WR_ERR | ||
| NONE | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | ||
| 0h | 0h | 0h | 0h | 0h | 0h | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:5 | RESERVED | NONE | 0h | Reserved |
| 4 | FLC_DON | R/W1TC | 0h | The ~iflc_don bit indicates a FLC has completed the transfer to the FLC range. Write 1 to clear the ~iflc_don status after interrupt has been serviced (raw status gets cleared, i.e. even if not enabled). Writing a 0 has no effect to this field. |
| 3 | FLC_WRERR | R/W1TC | 0h | The ~iflc_wrerr bit indicates a write error from FLC range has occurred and the FLC is logically disabled while this bit is a '1'. Write 1 to clear the ~iflc_wrerr status after interrupt has been serviced (raw status gets cleared, i.e. even if not enabled). Writing a 0 has no effect to this field. |
| 2 | FLC_RDERR | R/W1TC | 0h | The ~iflc_rderr bit indicates a read error from FLC range has occurred and the FLC is logically disabled while this bit is a '1'. Write 1 to clear the ~iflc_rderr status after interrupt has been serviced (raw status gets cleared, i.e. even if not enabled). Writing a 0 has no effect to this field. |
| 1 | WR_HIT | R/W1TC | 0h | The ~iwr_hit bit indicates a write to the cacheable range has occurred potentially causing a coherency issue and the RL2 is logically disabled while this bit is a '1'. Write 1 to clear the ~iwr_hit status after interrupt has been serviced (raw status gets cleared, i.e. even if not enabled). Writing a 0 has no effect to this field. |
| 0 | WR_ERR | R/W1TC | 0h | The ~iwr_err bit indicates a write error has occurred to the remote cache data storage memory and the RL2 is logically disabled while this bit is a '1'. Write 1 to clear the ~iwr_err status after interrupt has been serviced (raw status gets cleared, i.e. even if not enabled). Writing a 0 has no effect to this field. |