SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
CRC Interrupt Enable Set Register
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| Instance Name | Physical Address |
|---|---|
| MCRC64_0 | 3030 0018h + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | CH4_TIME_OUT_ENS_ | CH4_UNDERENS | CH4_OVERENS | CH4_CRC_FAILENS | CH4_CCITENS | ||
| NONE | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | ||
| 0h | 0h | 0h | 0h | 0h | 0h | ||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | CH3_TIME_OUT_ENS | CH3_UNDERENS | CH3_OVERENS | CH3_CRC_FAILENS | CH3_CCITENS | ||
| NONE | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | ||
| 0h | 0h | 0h | 0h | 0h | 0h | ||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | CH2_TIME_OUT_ENS_ | CH2_UNDERENS | CH2_OVERENS | CH2_CRC_FAILENS | CH2_CCITENS | ||
| NONE | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | ||
| 0h | 0h | 0h | 0h | 0h | 0h | ||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | CH1_TIME_OUT_ENS_ | CH1_UNDERENS | CH1_OVERENS | CH1_CRC_FAILENS | CH1_CCITENS | ||
| NONE | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | ||
| 0h | 0h | 0h | 0h | 0h | 0h | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:29 | RESERVED | NONE | 0h | Reserved |
| 28 | CH4_TIME_OUT_ENS_ | R/W1TS | 0h | Channel 4 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout Interrupt disable 1 = Timeout Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Timeout Interrupt enable |
| 27 | CH4_UNDERENS | R/W1TS | 0h | Channel 4 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun Interrupt disable 1 = Underrun Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Underrun Interrupt enable |
| 26 | CH4_OVERENS | R/W1TS | 0h | Channel 4 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun Interrupt disable 1 = Overrun Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Overrun Interrupt enable |
| 25 | CH4_CRC_FAILENS | R/W1TS | 0h | Channel 4 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail Interrupt disable 1 = CRC Fail Interrupt enable User and privileged mode write: 0 = Has no effect 1 = CRC Fail Interrupt enable |
| 24 | CH4_CCITENS | R/W1TS | 0h | Channel 4 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Compression Complete Interrupt disable 1 = Compression Complete Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Compression Complete Interrupt enable |
| 23:21 | RESERVED | NONE | 0h | Reserved |
| 20 | CH3_TIME_OUT_ENS | R/W1TS | 0h | Channel 3 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout Interrupt disable 1 = Timeout Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Timeout Interrupt enable |
| 19 | CH3_UNDERENS | R/W1TS | 0h | Channel 3 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun Interrupt disable 1 = Underrun Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Underrun Interrupt enable |
| 18 | CH3_OVERENS | R/W1TS | 0h | Channel 3 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun Interrupt disable 1 = Overrun Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Overrun Interrupt enable |
| 17 | CH3_CRC_FAILENS | R/W1TS | 0h | Channel 3 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail Interrupt disable 1 = CRC Fail Interrupt enable User and privileged mode write: 0 = Has no effect 1 = CRC Fail Interrupt enable |
| 16 | CH3_CCITENS | R/W1TS | 0h | Channel 3 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Compression Complete Interrupt disable 1 = Compression Complete Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Compression Complete Interrupt enable |
| 15:13 | RESERVED | NONE | 0h | Reserved |
| 12 | CH2_TIME_OUT_ENS_ | R/W1TS | 0h | Channel 2 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout Interrupt disable 1 = Timeout Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Timeout Interrupt enable |
| 11 | CH2_UNDERENS | R/W1TS | 0h | Channel 2 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun Interrupt disable 1 = Underrun Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Underrun Interrupt enable |
| 10 | CH2_OVERENS | R/W1TS | 0h | Channel 2 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun Interrupt disable 1 = Overrun Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Overrun Interrupt enable |
| 9 | CH2_CRC_FAILENS | R/W1TS | 0h | Channel 2 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail Interrupt disable 1 = CRC Fail Interrupt enable User and privileged mode write: 0 = Has no effect 1 = CRC Fail Interrupt enable |
| 8 | CH2_CCITENS | R/W1TS | 0h | Channel 2 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Compression Complete Interrupt disable 1 = Compression Complete Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Compression Complete Interrupt enable |
| 7:5 | RESERVED | NONE | 0h | Reserved |
| 4 | CH1_TIME_OUT_ENS_ | R/W1TS | 0h | Channel 1 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout Interrupt disable 1 = Timeout Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Timeout Interrupt enable |
| 3 | CH1_UNDERENS | R/W1TS | 0h | Channel 1 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun Interrupt disable 1 = Underrun Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Underrun Interrupt enable |
| 2 | CH1_OVERENS | R/W1TS | 0h | Channel 1 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun Interrupt disable 1 = Overrun Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Overrun Interrupt enable |
| 1 | CH1_CRC_FAILENS | R/W1TS | 0h | Channel 1 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail Interrupt disable 1 = CRC Fail Interrupt enable User and privileged mode write: 0 = Has no effect 1 = CRC Fail Interrupt enable |
| 0 | CH1_CCITENS | R/W1TS | 0h | Channel 1 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Compression Complete Interrupt disable 1 = Compression Complete Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Compression Complete Interrupt enable |