SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Device Write Instruction Configuration Register
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| Instance Name | Physical Address |
|---|---|
| FSS0 | 0FC4 0008h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| WR_INSTR_RESV4_FLD | DUMMY_WR_CLK_CYCLES_FLD | ||||||
| R | R/W | ||||||
| 0h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| WR_INSTR_RESV3_FLD | DATA_XFER_TYPE_EXT_MODE_FLD | ||||||
| R | R/W | ||||||
| 0h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| WR_INSTR_RESV2_FLD | ADDR_XFER_TYPE_STD_MODE_FLD | WR_INSTR_RESV1_FLD | WEL_DIS_FLD | ||||
| R | R/W | R | R/W | ||||
| 0h | 0h | 0h | 0h | ||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| WR_OPCODE_FLD | |||||||
| R/W | |||||||
| 2h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:29 | WR_INSTR_RESV4_FLD | R | 0h | Reserved |
| 28:24 | DUMMY_WR_CLK_CYCLES_FLD | R/W | 0h | Dummy Write Clock Cycles: Number of dummy clock cycles required by device for write instruction. |
| 23:18 | WR_INSTR_RESV3_FLD | R | 0h | Reserved |
| 17:16 | DATA_XFER_TYPE_EXT_MODE_FLD | R/W | 0h | Data Transfer Type for Standard SPI modes: 0 : SIO mode data is shifted to the device on DQ0 only and from the device on DQ1 only 1 : Used for Dual Input/Output instructions. For data transfers, DQ0 and DQ1 are used as both inputs and outputs. 2 : Used for Quad Input/Output instructions. For data transfers, DQ0,DQ1,DQ2 and DQ3 are used as both inputs and outputs. 3 : Used for Quad Input/Output instructions. For data transfers, DQ[7:0] are used as both inputs and outputs. |
| 15:14 | WR_INSTR_RESV2_FLD | R | 0h | Reserved |
| 13:12 | ADDR_XFER_TYPE_STD_MODE_FLD | R/W | 0h | Address Transfer Type for Standard SPI modes: 0 : Addresses can be shifted to the device on DQ0 only 1 : Addresses can be shifted to the device on DQ0 and DQ1 only 2 : Addresses can be shifted to the device on DQ0, DQ1, DQ2 and DQ3 3 : Addresses can be shifted to the device on DQ[7:0] |
| 11:9 | WR_INSTR_RESV1_FLD | R | 0h | Reserved |
| 8 | WEL_DIS_FLD | R/W | 0h | WEL Disable: This is to turn off automatic issuing of WEL Command before write operation for DAC or INDAC |
| 7:0 | WR_OPCODE_FLD | R/W | 2h | Write Opcode |