SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Traffic monitoring bus probes are deployed at strategic points in the system interconnect and support the following capabilities:
The below table details the locations in the system interconnect that are probed:
| Probe Point | Bus Monitoring Details |
|---|---|
| C7XSS0 Deep Learning Accelerator SDMA Target | Monitors traffic to DLA SDMA port |
| C7XSS1 Deep Learning Accelerator SDMA Target | Monitors traffic to DLA SDMA port |
| C7XSS0 Deep Learning Accelerator MDMA Initiator | Monitors traffic initiated by DLA MDMA |
| C7XSS1 Deep Learning Accelerator MDMA Initiator | Monitors traffic initiated by DLA MDMA |
| R5SS0 :: cpu0 rmst initiator | Monitors R5 read port |
| R5SS0 :: cpu0 wmst initiator | Monitors R5 write port |
| R5SS0 :: cpu1 rmst initiator | Monitors R5 read port |
| R5SS0 :: cpu1 wmst initiator | Monitors R5 write port |
| R5SS1 :: cpu0 rmst initiator | Monitors R5 read port |
| R5SS1 :: cpu0 wmst initiator | Monitors R5 write port |
| R5SS1 :: cpu1 rmst initiator | Monitors R5 read port |
| R5SS1 :: cpu1 wmst initiator | Monitors R5 write port |
| FSS OSPI0 Target | Monitors traffic to FSS |
| FSS OSPI1 Target | Monitors traffic to FSS |
| FSS of ul OSPI1 Target | Monitors traffic to FSS |
| OCSRAM Bank 0 | Monitors traffic to OCSRAM Bank 0 |
| OCSRAM Bank 1 | Monitors traffic to OCSRAM Bank 1 |
| OCSRAM Bank 2 | Monitors traffic to OCSRAM Bank 2 |
| OCSRAM Bank 3 | Monitors traffic to OCSRAM Bank 3 |
| OCSRAM Bank 4 | Monitors traffic to OCSRAM Bank 4 |
| OCSRAM Bank 5 | Monitors traffic to OCSRAM Bank 5 |
| Audio CBASS targets | Monitors traffic to these targets: MCASP# AASRC# ATL# |
| Peripheral CBASS Targets | Monitors traffic to these targets: ECAP# EQEP# I2C# MCAN# SPI# UART# |
| WKUP CBASS Targets | Monitors traffic from MAIN to WKUP, including these targets: WKUP_GTC WKUP_R5F WKUP_TIMER# WKUP_RTI WKUP_I2C# WKUP_CTRL_MMR0 WKUP_VTM0 |
| Infrastructure CBASS Targets | Monitors traffic to these targets: CMP_EVENT_INTROUTER CTRL_MMR DCC# DDPA DFTSS ESM PSRAM256x32 GPIO0 GPIO1 EFUSE GPIOMUX_INTROUTER PADCFG_CTRL_MMR0 PLL_MMR0 PLLCTRL PSC TIMESYNC_EVENT_ROUTE |