SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
In group mode data transfer for all the channels of group number N is shown in ASRC Group Mode Audio Data Write for Channels of Group N and ASRC Group Mode Audio Data Read from Channels of Group N.
Figure 12-6 ASRC Group Mode Audio Data Write for Channels of Group N
Figure 12-7 ASRC Group Mode Audio Data Read from Channels of Group NIt is not required for the device EDMA to service an event in one cycle as it may be busy with other transfers also. If EDMA channel is shared between more than one channels or groups, then it can queue the events and service whenever it has the resources available.
For each ingrp_evt[N], that is infifo event for group N, ASRC ensures that there is space available for at least INFIFO_THRESHOLD number of samples in the INFIFO of all the channels of that group. This INFIFO_THRESHOLD value can be set in ASRC_GFFCTRL_0[7:0] INFIFO_THRESHOLD register bitfield of that particular group. In this mode one sample is written in each of the channels of that group. The EDMA will update the adress to follow the channel number sequence of that group. This step is repeated INFIFO_THRESHOLD number of times to fill in INFIFO_THRESHOLD number of samples in each channel of that particular group.
For each outgrp_evt[N], that is outfifo event for group N, ASRC ensures that there is at least OUTFIFO_THRESHOLD number of samples available in OUTFIFO of all the channels of that group. This OUTFIFO_THRESHOLD value can be set in ASRC_GFFCTRL_0[23:16] OUTFIFO_THRESHOLD register bitfield of that particular group. In this mode one sample is read from all the channels of that group. The EDMA will update the address to follow the channel number sequence of that group. This step is repeated OUTFIFO_THRESHOLD number of times to drain OUTFIFO_THRESHOLD number of samples from each channel of that particular group.