SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The Host Driver can get status of the Host Controller from this 32-bit read-only register
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| Instance Name | Physical Address |
|---|---|
| MMCSD0 | 0FA0 0024h |
| 32 | 31 | 30 | 29 | 28 | 27 | 26 | 25 |
| UHS2_IF_DETECTION | UHS2_IF_LANE_SYNC | UHS2_DORMANT | SUB_COMMAND_STS | CMD_NOT_ISS_BY_ERR | RESERVED | SDIF_CMDIN | |
| R | R | R | R | R | NONE | R | |
| 0h | 0h | 0h | 0h | 0h | 0h | 1h | |
| 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 |
| SDIF_DAT3IN | SDIF_DAT2IN | SDIF_DAT1IN | SDIF_DAT0IN | WRITE_PROTECT | CARD_DETECT | CARD_STATE_STABLE | CARD_INSERTED |
| R | R | R | R | R | R | R | R |
| 1h | 1h | 1h | 1h | 0h | 0h | 0h | 0h |
| 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 |
| RESERVED | BUF_RD_ENA | BUF_WR_ENA | RD_XFER_ACTIVE | WR_XFER_ACTIVE | |||
| NONE | R | R | R | R | |||
| 0h | 0h | 0h | 0h | 0h | |||
| 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 |
| SDIF_DAT7IN | SDIF_DAT6IN | SDIF_DAT5IN | SDIF_DAT4IN | RETUNING_REQ | DATA_LINE_ACTIVE | INHIBIT_DAT | INHIBIT_CMD |
| R | R | R | R | R | R | R | R |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | UHS2_IF_DETECTION | R | 0h | This status indicates whether a card supports UHS-II IF. This status is enabled by setting UHS-II Interface Enable to 1 in the Host Control 2 regis-ter. UHS-II interface initialization is activated by setting SD Clock Enable in the Clock Control reg-ister. Host Controller drives STB.L on D0 lanefrom EIDL state and waits for receiving STB.L on D1 lane. This bit is set to 1 if STB.L is detected on D1 lane. Host Controller shall compensate latency from setting SD Clock Enable to output STB.L on D0 lane when reading this status [Refer to Figure 3-35 about details of this method]. This bit may be read any time after setting SD Clock Enable for faster UHS-II IF detection but Host Driver shall check this status at least 200us period from set- ting SD Clock Enable until detecting UHS-II IF. After UHS-II IF is detected, this bit is cleared by when EIDL is detected on D0 lane, UHS-II Inter-face Enable is set to 0 or Host full reset is exe-cuted. '0' UHS-II IF is not detected '1' UHS-II IF is detected Reset Source: vbus_amod_g_rst_n |
| 30 | UHS2_IF_LANE_SYNC | R | 0h |
This status indicates whether lane is synchronized in UHS-II mode. This status is enabled by setting UHS-II Interface Enable to 1 in the Host Control 2 register. On detecting UHS-II Interface [D31=1], Host Controller provides SYN LSS on D0 lane and waits for receiving SYN LSS on D1 lane. If SYN LSS is detected on D1 lane, Host Controller pro-vides LIDL LSS on D0 lane and waits for receiving LIDL LSS on D1 lane.
In case of Version 4.00, this bit indicates comple-tion of Device PHY Initialization by detecting LIDL LSS on D1 lane.From Version 4.10, Host Controller may imple-ment a specific PHY verification method and PHY
Initialization Failure can be indicated by keeping this bit to 0 even LIDL LSS is detected on D1 lane.Host Driver detects PHY Initialization Failure by timeout.This bit is cleared by when D0 lane is set to EIDL,UHS-II Interface Enable is set to 0 or executes Host full reset.
1 UHS-II PHY is initialized 0 UHS-II PHY is not initialized |
| 29 | UHS2_DORMANT | R | 0h |
This status indicates whether UHS-II Ianes enterDormant state. This function is enabled by setting UHS-II Interface Enable to 1 in the Host Control 2 register. On issuing GO_DORMAT_STATE com-mand, Go Dormant Command [111b]; is set to Command type in the UHS-II Command register.This command type acts as a trigger to enterlanes into dormant state. Host Controller provides STB.H and EIDL on D0 lane and waits for receiv-ing STB.H and EIDL on D1 lane. This bit is set to 1 after the time of T_DMT_ENTRY [750 RCLK cycle] or more from detecting EIDL on D1 lane.
RCLK may be stopped in dormant state, by setting SD Clock Enable to 0 in the Clock Control register while In Dormant State bit is set to 1. On writingClock Control register with setting SD Clock Enable to 1, Host Controller wakes lanes to exit Dormant State and In Dormant State is set to 0. In case of the card enters Hibernate Mode [RCLK is stopped], Host Driver may turn off VDD1 by clearing SD Bus Power for VDD1 bit in the Power Control register. Host Controller shall turn off VDD1 after stopping RCLK. This bit is cleared by when Host Controller drives STB.L on D0 lane, UHS-II Interface Enable is set to 0 or executesHost full reset.
1 In DORMANT state 0 Not in DORMANT state |
| 28 | SUB_COMMAND_STS | R | 0h | The Command register and Response register are commonly used for main command and sub command. This status is used to distinguish which response error statuses, main command or sub command, indicated in the Error Interrupt Status register or in the UHS-II Error Interrupt Status register. Refer to Section 1.17 about details of response error statuses. Just before reading of this register, the Sub Command Flag of the Command register or the UHS-II Command register is copied to this status. This status is effective not only when Response Error interrupt is generated but also when data error interrupt is generated with Command Not Issued by Error [D27 of this register] or Auto CMD Error interrupt is generated with Command Not Issued by Error by Auto CMD12 in the Auto CMD Error Status register. 1 - Sub Command Status 0 - Main Command Status Reset Source: vbus_amod_g_rst_n |
| 27 | CMD_NOT_ISS_BY_ERR | R | 0h | Setting of this status indicates that a command cannot be issued due to an error except Auto CMD12 error. [Equivalent error status by Auto CMD12 error is defined as Command Not Issued By Auto CMD12 Error in the Auto CMD Error Status register.] This status is set to 1 when Host Controller cannot issue a command after setting Command register or UHS-II Command register.Refer to Section 3.10 about 2L-HD error case inUHS-II mode.Sub Command Status [D28] indicates which command is not issued [main or sub]. 1 - Command cannot be issued 0 - No error for issuing a command Reset Source: vbus_amod_g_rst_n |
| 26:25 | RESERVED | NONE | 0h | Reserved |
| 24 | SDIF_CMDIN | R | 1h | This status is used to check DAT line level to recover from errors, and for debugging. Reset Source: vbus_amod_g_rst_n |
| 23 | SDIF_DAT3IN | R | 1h | This status is used to check DAT line level to recover from errors, and for debugging. This is especially useful in detecting the busy signal level from DAT[3]. Reset Source: vbus_amod_g_rst_n |
| 22 | SDIF_DAT2IN | R | 1h | This status is used to check DAT line level to recover from errors, and for debugging. This is especially useful in detecting the busy signal level from DAT[2]. Reset Source: vbus_amod_g_rst_n |
| 21 | SDIF_DAT1IN | R | 1h | This status is used to check DAT line level to recover from errors, and for debugging. This is especially useful in detecting the busy signal level from DAT[1]. Reset Source: vbus_amod_g_rst_n |
| 20 | SDIF_DAT0IN | R | 1h | This status is used to check DAT line level to recover from errors, and for debugging. This is especially useful in detecting the busy signal level from DAT[0]. Reset Source: vbus_amod_g_rst_n |
| 19 | WRITE_PROTECT | R | 0h |
The Write Protect Switch is supported for memory and combo cards.This bit reflects the SDWP# pin.
1 Write enabled (SDWP# = 0) 0 Write protected (SDWP# = 1) |
| 18 | CARD_DETECT | R | 0h | This bit reflects the inverse value of the SDCD# pin. '0' No Card present [SDCD# = 1] '1' Card present [SDCD# = 0] Reset Source: vbus_amod_g_rst_n |
| 17 | CARD_STATE_STABLE | R | 0h | This bit is used for testing. If it is 0, the Card Detect Pin Level is not stable. If this bit is set to 1,it means the Card Detect Pin Level is stable. The Software Reset For All in the Software Reset Register shall not affect this bit. '0' Reset of Debouncing '1' No Card or Inserted Reset Source: vbus_amod_g_rst_n |
| 16 | CARD_INSERTED | R | 0h | This bit indicates whether a card has been inserted. Changing from 0 to 1 generates a Card Insertion interrupt in the Normal Interrupt Status register and changing from 1 to 0 generates a Card Removal Interrupt in the Normal Interrupt Status register. The Software Reset For All in the Software Reset register shall not affect this bit. If a Card is removed while its power is on and its clock is oscillating, the HC shall clear SD Bus Power in the Power Control register and SD Clock Enable in the Clock control register. In addition the HD should clear the HC by the Software Reset For All in Software register. The card detect is active regardless of the SD Bus Power. '0' Reset or Debouncing or No Card '1' Card Inserted Reset Source: vbus_amod_g_rst_n |
| 15:12 | RESERVED | NONE | 0h | Reserved |
| 11 | BUF_RD_ENA | R | 0h |
This status is used for non-DMA read transfers.This read only flag indicates that valid data exists in the host side buffer status. If this bit is 1, readable data exists in the buffer. A change of this bit from 1 to 0 occurs when all the block data is read from the buffer. A change of this bit from 0 to 1 occurs when all the block data is ready in the buffer and generates the Buffer Read Ready Interrupt.
1 Read Enable 0 Read Disable |
| 10 | BUF_WR_ENA | R | 0h |
This status is used for non-DMA write transfers.This read only flag indicates if space is available for write data. If this bit is 1, data can be written to the buffer. A change of this bit from 1 to 0 occurs when all the block data is written to the buffer. A change of this bit from 0 to 1 occurs when top of block data can be written to the buffer and generates the Buffer Write Ready Interrupt.
1 Write Enable 0 Write Disable |
| 9 | RD_XFER_ACTIVE | R | 0h |
This status is used for detecting completion of a read transfer.
This bit is set to 1 for either of the following conditions:
After the end bit of the read command.
When writing a 1 to continue Request in the Block Gap Control register to restart a read transfer.
This bit is cleared to 0 for either of the following conditions:
When the last data block as specified by block length is transferred to the system.
When all valid data blocks have been transferred to the system and no current block transfers are being sent as a result of the Stop At Block Gap Request set to 1. A transfer complete interrupt is generated when this bit changes to 0.
'0' No valid data
'1' Transferring data
1 Transferring data 0 No valid data |
| 8 | WR_XFER_ACTIVE | R | 0h |
This status indicates a write transfer is active. If this bit is 0, it means no valid write data exists in the HC.
This bit is set in either of the following cases:
After the end bit of the write command.
When writing a 1 to Continue Request in the Block Gap Control register to restart a write transfer.
This bit is cleared in either of the following cases:
After getting the CRC status of the last data block as specified by the transfer count [Single or Multiple]
After getting a CRC status of any block where data transmission is about to be stopped by a Stop At Block Gap Request.
During a write transaction, a Block Gap Event interrupt is generated when this bit is changed to 0, as a result of the Stop At Block Gap Request being set. This status is useful for the HD in determining when to issue commands during write busy.
1 Transferring data 0 No valid data |
| 7 | SDIF_DAT7IN | R | 0h | This status is used to check DAT line level to recover from errors, and for debugging. Reset Source: vbus_amod_g_rst_n |
| 6 | SDIF_DAT6IN | R | 0h | This status is used to check DAT line level to recover from errors, and for debugging. Reset Source: vbus_amod_g_rst_n |
| 5 | SDIF_DAT5IN | R | 0h | This status is used to check DAT line level to recover from errors, and for debugging. Reset Source: vbus_amod_g_rst_n |
| 4 | SDIF_DAT4IN | R | 0h | This status is used to check DAT line level to recover from errors, and for debugging. Reset Source: vbus_amod_g_rst_n |
| 3 | RETUNING_REQ | R | 0h |
Host Controller may request Host Driver to execute re-tuning sequence by setting this bit when the data window is shifted by temperature drift and a tuned sampling point does not have a good margin to receive correct data.
This bit is cleared when a command is issued with setting Execute Tuning in the Host Control 2 register.
Changing of this bit from 0 to 1 generates Re-Tuning Event. Refer to Normal Interrupt registers for more detail. This bit isn't set to 1 if Sampling Clock Select in the Host Control 2 register is set to 0 [using fixed sampling clock].
1 Sampling clock needs re-tuning 0 Fixed or well tuned sampling clock |
| 2 | DATA_LINE_ACTIVE | R | 0h |
This bit indicates whether one of the DAT line on SD bus is in use.
1 DAT line active 0 DAT line inactive |
| 1 | INHIBIT_DAT | R | 0h | This status bit is generated if either the DAT Line Active or the Read transfer Active is set to 1. If this bit is 0, it indicates the HC can issue the next SD command. Commands with busy signal belong to Command Inhibit [DAT] [ex. R1b, R5b type]. Changing from 1 to 0 generates a Transfer Complete interrupt in the Normal interrupt status register. Note: The SD Host Driver can save registers in the range of 000-00Dh for a suspend transaction after this bit has changed from 1 to 0. '0' Can issue command which uses the DAT line '1' Cannot issue command which uses the DATline Reset Source: vbus_amod_g_rst_n |
| 0 | INHIBIT_CMD | R | 0h | SD Mode If this bit is 0, it indicates the CMD line is not in use and the HC can issue a SD command using the CMD line. This bit is set immediately after the Command register [00Fh] is written. This bit is cleared when the command response is received. Even if the Command Inhibit [DAT] is set to 1, Commands using only the CMD line can be issued if this bit is 0. Changing from 1 to 0 gener- ates a Command complete interrupt in the Normal Interrupt Status register. If the HC cannot issuethe command because of a command conflict error or because of Command Not Issued By Auto CMD12 Error, this bit shall remain 1 and the Com- mand Complete is not set. Status issuing Auto CMD12 is not read from this bit. Auto CMD12 and Auto CMD23 consist of two responses. In this case, this bit is not cleared by the response of CMD12 or CMD23 but cleared by the response of a read/write command. Status issuing Auto CMD12 is not read from this bit. So if a command is issued during Auto CMD12 opera- tion, Host Controller shall manage to issue two commands: CMD12 and a command set by Com-mand register. UHS-II Mode This bit is 0 means that a command packet can be issued by the Host Controller. While this bit is set to 1, which means the Host Controller is not ready to issue a next command, Host Driver shall not write the registers from UHS-II BlockSize [Offset 080h] to the UHS-II Command [Offset 09Eh]. Changing from 1 to 0 generates a Command Complete Interrupt in the Normal Interrupt Status-register. 1- Host Controller is not ready to issue a com-mand 0 - Host Controller is ready to issue a command Version 4.10 adds a new control to prevent error statuses from overwriting by receipt of a next com-mand. This status keeps indicating 1 while any of response error statuses is set to 1 [as described in Section 1.17], Command Not Issued by Error in this register is set to 1 or Command Not Issued by Auto CMD12 Error in the Auto CMD Error Status register is set to 1. Software Reset For CMD Lineis used to clear the error statuses above and this status. Reset Source: vbus_amod_g_rst_n |