SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
SRAM Partition Configuration Register
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| Instance Name | Physical Address |
|---|---|
| FSS0 | 0FC4 0018h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| SRAM_PARTITION_RESV_FLD | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| SRAM_PARTITION_RESV_FLD | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| SRAM_PARTITION_RESV_FLD | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ADDR_FLD | |||||||
| R/W | |||||||
| 80h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:8 | SRAM_PARTITION_RESV_FLD | R | 0h | Reserved |
| 7:0 | ADDR_FLD | R/W | 80h | Indirect Read Partition Size: Defines the size of the indirect read partition in the SRAM, in units of SRAM locations. By default, half of the SRAM is reserved for indirect read operation, and half for indirect write. The size of this register will scale with the depth of the SRAM. |