SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Global Host FIFO DMA High-Low Priority Ratio Register This register specifies the relative priority of the SS FIFOs with respect to the HS/FSLS FIFOs. The DMA arbiter prioritizes the HS/FSLS round-robin arbiter group every DMA High-Low Priority Ratio grants as indicated in the register separately for TX and RX. To illustrate, consider that all FIFOs are requesting access simultaneously, and the ratio is 4. SS gets priority for 4 packets, HS/FSLS gets priority for 1 packet, SS gets priority for 4 packets, HS/FSLS gets priority for 1 packet, and so on. If FIFOs from both speed groups are not requesting access simultaneously then, - if SS got grants 4 out of the last 4 times, then HS/FSLS get the priority on any future request. - if HS/FSLS got the grant last time, SS gets the priority on the next request. - if there is a valid request on either SS or HS/FSLS, a grant is always awarded. there is no idle. This register is present if the controller is configured to operate in host mode (includes DRD).
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| Instance Name | Physical Address |
|---|---|
| USB0 | 3100 C624h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED_31_13 | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED_31_13 | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED_31_13 | HSTRXFIFO | ||||||
| R | R/W | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED_7_5 | HSTTXFIFO | ||||||
| R | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:13 | RESERVED_31_13 | R | 0h | Reserved |
| 12:8 | HSTRXFIFO | R/W | 0h | Host RXFIFO DMA High-Low Priority Reset Source: rst_mod_g_rst_n |
| 7:5 | RESERVED_7_5 | R | 0h | Reserved |
| 4:0 | HSTTXFIFO | R/W | 0h | Host TXFIFO DMA High-Low Priority Reset Source: rst_mod_g_rst_n |