SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register provides information about the current state of the control lines from the modem, data set or peripheral device to the LH. It also indicates when a control input from the modem changes state.
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| Instance Name | Physical Address |
|---|---|
| UART0 | 0280 0018h |
| UART1 | 0281 0018h |
| UART2 | 0282 0018h |
| UART3 | 0283 0018h |
| UART4 | 0284 0018h |
| UART5 | 0285 0018h |
| UART6 | 0286 0018h |
| WKUP_UART0 | 2B30 0018h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED_24 | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED_24 | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED_24 | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| NCD_STS | NRI_STS | NDSR_STS | NCTS_STS | DCD_STS | RI_STS | DSR_STS | CTS_STS |
| R | R | R | R | R | R | R | R |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:8 | RESERVED_24 | R | 0h | |
| 7 | NCD_STS | R | 0h | This bit is the complement of the DCD* input. In loop-back mode it is equivalent to MCR[3] Reset Source: mod_g_arstn |
| 6 | NRI_STS | R | 0h | This bit is the complement of the RI* input. In loop-back mode it is equivalent to MCR[2] Reset Source: mod_g_arstn |
| 5 | NDSR_STS | R | 0h | This bit is the complement of the DSR* input. In loop-back mode, it is equivalent to MCR[0] Reset Source: mod_g_arstn |
| 4 | NCTS_STS | R | 0h | This bit is the complement of the CTS* input. In loop-back mode it is equivalent to MCR[1] Reset Source: mod_g_arstn |
| 3 | DCD_STS | R | 0h | Indicates that DCD* input [or MCR[3] in loop back] has changed. Cleared on a read. Reset Source: mod_g_arstn |
| 2 | RI_STS | R | 0h | Indicates that RI* input [or MCR[2] in loop back] has changed state from low to high. Cleared on a read. Reset Source: mod_g_arstn |
| 1 | DSR_STS | R | 0h | 1 Indicates that DSR* input (or MCR[0] in
loop back) has changed state. Cleared on a
read |
| 0 | CTS_STS | R | 0h | 1 Indicates that CTS* input (or MCR[1] in
loop back) has changed state. Cleared on a
read. |