SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The State Data Registers contain the current working state of the Tx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was reported by the channel. These registers should not be accessed without reason while the BCDMA is operating as accesses will cause performance to decrease as these MMRs are just providing a window into the actual state RAM
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| Instance Name | Physical Address |
|---|---|
| DMASS0_BCDMA_0 | 4C00 0080h + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| STATE_INFO | |||||||
| R/NA | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| STATE_INFO | |||||||
| R/NA | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| STATE_INFO | |||||||
| R/NA | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| STATE_INFO | |||||||
| R/NA | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:0 | STATE_INFO | R/NA | 0h | See Tx state mapping table Reset Source: rst_mod_g_rst_n |