SPRUJC6 User guide

SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1

2.2.16.1 MCASP_ACLKRCTL Register (Offset = 70h) [reset = 20h]

The receive clock control register (ACLKRCTL) configures the receive bit clock (ACLKR) and the receive clock generator.

Table 14-11119 Instance Table

Figure 14-5509 MCASP_ACLKRCTL Name Register

Table 14-11120 MCASP_ACLKRCTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31:21	RESERVED86	R/W	0h
20	BUSY	R/W	0h	Status: logical OR of DIVBUSY, ADJBUSY
19	DIVBUSY	R/W	0h	Status: divide ratio change in progress
18	ADJBUSY	R/W	0h	Status: one-shot adjustment in progress
17:16	CLKRADJ	W	0h	CLKRDIV one-shot adjustment
15:8	RESERVED85	R/W	0h
7	CLKRP	R/W	0h	Receive bitstream clock polarity select bit. 0 Falling edge. Receiver samples data on the falling edge of the serial clock, so the external transmitter driving this receiver must shift data out on the rising edge of the serial clock. 1 Rising edge. Receiver samples data on the rising edge of the serial clock, so the external transmitter driving this receiver must shift data out on the falling edge of the serial clock.
6	RESERVED84	R	0h
5	CLKRM	R/W	1h	Receive bit clock source bit. Note that this bit does not have any effect, if ACLKXCTL.ASYNC = 0. 0 External receive clock source from ACLKR pin. 1 Internal receive clock source from output of programmable bit clock divider.
4:0	CLKRDIV	R/W	0h	Receive bit clock divide ratio bits determine the divide-down ratio from AHCLKR to ACLKR. Note that this bit does not have any effect, if ACLKXCTL.ASYNC = 0. 0 Divide-by-1. 1 Divide-by-2. 2 Divide-by-3 to divide-by-32 from 2h to 1Fh.