SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
| Offset | Length | Register Name | FSS1_OSPI_0 Physical Address |
|---|---|---|---|
| 0h | 32 | ECC_AGGR_REV | 0072 3000h |
| 8h | 32 | ECC_AGGR_VECTOR | 0072 3008h |
| Ch | 32 | ECC_AGGR_STAT | 0072 300Ch |
| 10h | 32 | ECC_AGGR_RESERVED_SVBUS_J | 0072 3010h + formula |
| 3Ch | 32 | ECC_AGGR_SEC_EOI_REG | 0072 303Ch |
| 40h | 32 | ECC_AGGR_SEC_STATUS_REG0 | 0072 3040h |
| 80h | 32 | ECC_AGGR_SEC_ENABLE_SET_REG0 | 0072 3080h |
| C0h | 32 | ECC_AGGR_SEC_ENABLE_CLR_REG0 | 0072 30C0h |
| 13Ch | 32 | ECC_AGGR_DED_EOI_REG | 0072 313Ch |
| 140h | 32 | ECC_AGGR_DED_STATUS_REG0 | 0072 3140h |
| 180h | 32 | ECC_AGGR_DED_ENABLE_SET_REG0 | 0072 3180h |
| 1C0h | 32 | ECC_AGGR_DED_ENABLE_CLR_REG0 | 0072 31C0h |
| 200h | 32 | ECC_AGGR_AGGR_ENABLE_SET | 0072 3200h |
| 204h | 32 | ECC_AGGR_AGGR_ENABLE_CLR | 0072 3204h |
| 208h | 32 | ECC_AGGR_AGGR_STATUS_SET | 0072 3208h |
| 20Ch | 32 | ECC_AGGR_AGGR_STATUS_CLR | 0072 320Ch |