SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Hardware Watchpoint Control Register This is the control and status register for hardware watchpoint resource.
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| Instance Name | Physical Address |
|---|---|
| C7X256V0_DEBUG | 0007 3400 0300h |
| C7X256V1_DEBUG | 0007 3800 0300h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| MANUAL | RESERVED_4 | ||||||
| R/W | R/W | ||||||
| 0h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED_4 | CRIT_ADDR_WR | CRIT_ADDR_RD | RESERVED_3 | CRIT_ADDR_SIZE | |||
| R/W | R/W | R/W | R/W | R/W | |||
| 0h | 0h | 0h | 0h | 0h | |||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| CRIT_ADDR_SIZE | CRIT_PROC | CRIT_VMID | CRIT_DCTXT | CRIT_ADDR | |||
| R/W | R/W | R/W | R/W | R/W | |||
| 0h | 0h | 0h | 0h | 0h | |||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED_2 | CONDITION | TRIGGERED | INTEREST | RESERVED | ENABLE | ||
| R/W | R/W | R/W | R/W | R/W | R/W | ||
| 0h | 0h | 0h | 0h | 0h | 0h | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | MANUAL | R/W | 0h | This bitfield provides a manual override to the generation of the hardware watchpoint trigger When set, the hardware watchpoint is continuously triggered |
| 30:22 | RESERVED_4 | R/W | 0h | reserved |
| 21 | CRIT_ADDR_WR | R/W | 0h | This bitfield configures if data write requests [stores] are monitored to determine a comparison match when the address comparison criteria is enabled |
| 20 | CRIT_ADDR_RD | R/W | 0h | This bitfield configures if data read requests [loads] are monitored to determine a comparison match when the address comparison criteria is enabled |
| 19 | RESERVED_3 | R/W | 0h | reserved |
| 18:12 | CRIT_ADDR_SIZE | R/W | 0h | This bitfield configures the size of the access used to determine a comparison match when the address comparison criteria is enabled ------0 : 8 bit acceses are not considered ------1 : 8 bit accesses are considered -----0- : 16-bit accesses are not considered -----1- : 16-bit accesses are considered ----0-- : 32-bit accesses are not considered ----1-- : 32-bit accesses are considered ---0--- : 64-bit accesses are not considered ---1--- : 64-bit accesses are considered --0---- : 128-bit accesses are not considered --1---- : 128-bit accesses are considered -0----- : 256-bit accesses are not considered -1----- : 256-bit accesses are considered 0------ : 512-bit accesses are not considered 1------ : 512-bit accesses are considered |
| 11 | CRIT_PROC | R/W | 0h | This bit designates if the processor state match criteria is used to determine a comparison match |
| 10 | CRIT_VMID | R/W | 0h | This bit designates if the VMID match criteria is used to determine a comparison match |
| 9 | CRIT_DCTXT | R/W | 0h | This bit designates if the debug context match criteria is used to determine a comparison match |
| 8 | CRIT_ADDR | R/W | 0h | This bit designates if the address comparison criteria is used to determine a comparison match |
| 7:5 | RESERVED_2 | R/W | 0h | reserved |
| 4 | CONDITION | R/W | 0h | This bit defines the trigger condition that results in the generation of a trigger |
| 3 | TRIGGERED | R/W | 0h | This bit indicates that the trigger condition has been met since the last time this bit was cleared |
| 2 | INTEREST | R/W | 0h | This bit configures the module to generate an AET event when triggered |
| 1 | RESERVED | R/W | 0h | reserved |
| 0 | ENABLE | R/W | 0h | This is the local enable for the hardware watchpoint module |