SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Figure 12-81 shows all of the MCSPI interface signals in controller mode.
Table 12-93 describes the MCSPI I/O signals in controller mode.
| Module Pin | Device Level Signal | I/O(1) | Description | Module Pin Reset Value(2) |
|---|---|---|---|---|
| MCU_MCSPIi(5) | ||||
| SPICLK | MCU_SPIi(5)_CLK | O | MCSPI Serial clock output for controller mode. | HiZ |
| SPIDAT[0] | MCU_SPIi(5)_D0 | O(3) | MCSPI Data I/O for controller mode. | HiZ |
| SPIDAT[1] | MCU_SPIi(5)_D1 | I(4) | MCSPI Data I/O for controller mode. | HiZ |
| SPIEN_[n] | MCU_SPIi(5)_CSi | O | MCSPI Chip-select i output for controller mode | HiZ |
| MCSPIi(5) | ||||
| SPICLK | SPIi(5)_CLK | O | MCSPI Serial clock output for controller mode. | HiZ |
| SPIDAT[0] | SPIi(5)_D0 | O(3) | MCSPI Data I/O for controller mode. | HiZ |
| SPIDAT[1] | SPIi(5)_D1 | I(4) | MCSPI Data I/O for controller mode. | HiZ |
| SPIEN_[n] | SPIi(5)_CSi | O | MCSPI Chip-select i output for controller mode | HiZ |
For SPIi(5)_CLK and MCU_SPIi(5)_CLK signals to work properly, the RXACTIVE bit of the appropriate MCU_PADCFG_CTRL_MMR_CFG0_PADCONFIGx/ MAIN_CTRL_MMR_CFG0_PADCONFIGy registers should be set to 0x1 because of retiming purposes.
For more information about device level signals (pull-up/down resistors, buffer type, multiplexing and others), see tables Pin Attributes and Pin Multiplexing in the device-specific Datasheet.