SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This is used in conjunction with Claim Tag Clear Register, CLAIMCLR. This register forms one half of the Claim Tag value. This location allows individual bits to be set, write, and returns the number of bits that can be set, read.
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| Instance Name | Physical Address |
|---|---|
| C7X256V0_DEBUG | 0007 3400 3FA0h |
| C7X256V0_DEBUG | 0007 3400 AFA0h |
| C7X256V0_DEBUG | 0007 3400 BFA0h |
| C7X256V1_DEBUG | 0007 3800 3FA0h |
| C7X256V1_DEBUG | 0007 3800 AFA0h |
| C7X256V1_DEBUG | 0007 3800 BFA0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | CLAIMSET | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:4 | RESERVED | NONE | 0h | Reserved |
| 3:0 | CLAIMSET | R/W | 0h | This claim tag bit is implemented |