SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The data on the serial data line (SDA) must be stable during the high period of the serial clock line. The high and low states of the data line can change only when the clock signal on the serial clock line (SCL) is low.
Figure 12-64 is an example of data validity requirements.
Figure 12-64 I2C Bit Transfer on the I2C Bus