SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The vbus comparator signals may be filtered by controlling these register values.
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| Instance Name | Physical Address |
|---|---|
| USB0 | 0F90 0614h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED31_9 | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED31_9 | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED31_9 | SESSVALID_BYPASS | ||||||
| R | R/W | ||||||
| 0h | 1h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SESSVALID_THRESH | RESERVED5_3 | VBUSVALID_BYPASS | VBUSVALID_THRESH | ||||
| R/W | R | R/W | R/W | ||||
| 0h | 0h | 1h | 0h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:9 | RESERVED31_9 | R | 0h | Reserved bits |
| 8 | SESSVALID_BYPASS | R/W | 1h | 0= use filter, 1= bypass filter Reset Source: cfg_srst_n |
| 7:6 | SESSVALID_THRESH | R/W | 0h | 00= 1us,01= 100us,10= 5ms,11= 50ms. 4 utmi_clk latency for sessvalid Reset Source: cfg_srst_n |
| 5:3 | RESERVED5_3 | R | 0h | Reserved bits |
| 2 | VBUSVALID_BYPASS | R/W | 1h | 0= use filter, 1= bypass filter for vbusvalid Reset Source: cfg_srst_n |
| 1:0 | VBUSVALID_THRESH | R/W | 0h | 00= 1us,01= 100us,10= 5ms,11= 50ms. 4 utmi_clk latency for vbusvalid Reset Source: cfg_srst_n |