SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Time-Base Status Register
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| Instance Name | Physical Address |
|---|---|
| EPWM0 | 2300 0002h |
| EPWM1 | 2301 0002h |
| EPWM2 | 2302 0002h |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED1 | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED1 | CTRMAX | SYNCI | CTRDIR | ||||
| R | R/W1TC | R/W1TC | R | ||||
| 0h | 0h | 0h | 0h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15:3 | RESERVED1 | R | 0h | Reserved |
| 2 | CTRMAX | R/W1TC | 0h | Time-Base Counter Max Latched Status Bit 0h Reading a 0h 1h Reading a 1h |
| 1 | SYNCI | R/W1TC | 0h | Input Synchronization Latched Status Bit 0h Writing a 0h 1h Reading a 1h |
| 0 | CTRDIR | R | 0h | Time-Base Counter Direction Status Bit At reset, the counter is frozen, therefore, this bit has no meaning To make this bit meaningful, you must first set the appropriate mode via TBCTL[CTRMODE] 0h Time-Base Counter is currently counting
down
1h Time-Base Counter is currently counting up |