The device contains a Device Manager (DM) to handle all of the low-level power management control of the device including the Low Power Mode transitions. A firmware is provided by Texas Instruments that includes all of the necessary functions to achieve low power modes. Inter-processor Communication (IPC) registers are available to communicate with the Device Manager so the user can provide certain configuration parameters based on the level of low power that is required.
- By default PMIC_LPM_EN must be pulled HIGH externally to power-up SoC (when used as PMIC ENABLE control). As soon as supplies are ON, the device drives HIGH on this signal.
- Device powers up with CANUART IO Daisy Chain mode disabled. CAN_ONLY_IO status (CANUART_WAKE_STAT*) will read '0' indicating that CANUART IO Daisy chain mode is not enabled. All PORx and HHV signals propage without any gating
- After MCU_PORz goes High, device boots-up as per BOOT Config pin setup
- DM SBL reads, CAN_ONLY_IO status to determine if the CAN ONLY IO daisy chain is enabled. Since this is the first boot-up, this status bit reads '0'.
- DM completes boot-up and configures device as per SBL code
- Device enters steady state operation
- At this point, if the application needs to enter CANUART IO mode, application first write the desired retention data to the Retention ROM, upon completion, the corresponding core shall perform a full cache writeback data, and perform a CPU fencing to the physical memory. Application shall ensure no other cores accessing the retention RAM. Then, DM kicks-off the IO daisy chain sequence to put the CANUART IOs in retention state. DM programs PADCFG MMRs to put IO in desired state (IO direction, IO level, Pulls), WUEN for wakup and writes into the WKUP MMR to set the global_wu_en bits. DM then writes to asserts ISOIN[0] control to a High.
- DM the programs CAN ONLY IO DAISY CHAIN WORD also known as Magic Word (CANUART_WAKE_OFF_MODE) . DM toggles the Load Enable bit High and Low (steps below). This latches the Magic Word in VDD_CAN domain. At this point, CAN_ONLY_IO signal (CANUART_WAKE_CTRL) must read as a '1'
- DM writes to CANUART_WAKE_STAT0 with Magic Word and CANUART_WAKE_CTRL_mw_load_en with 1
- DM polls to CANUART_WAKE_STAT1 for IORET mode to be set. This insures spacing for the async interface to write the correct Magic Word value
- DM writes to CANUART_WAKE_STAT0 with the !(Magic Word) and CANUART_WAKE_CTRL_mw_load_en with 0
- Once CAN_ONLY_IO is HIGH, it latches the ISOIN[0] control signal in the VDDU domain blocks and forces the porz and hhvz signals HIGH (inactive state).
- At the point the device is ready to support CAN Only IO mode
- DM writes into the pmic_en bit to '0'. This de-assers PMIC_LPM_EN from a High to a Low. PMIC detects this High to Low transition will power off SoC supplies. Note that VDDSHV_CAN and VDDU_CAN are still powered on.
- Now device should be in the lowers power mode with just the CANUART IOs in Daisy chain mode.
- Any event on these pins will cause an wakeup event out of CANUART IO daisy chain. This wakeup event forces the PMIC_LPM_EN to go HIGH. (PMCTRL_SYS register)
- PMIC detects this Low to High transition on PMIC_LPM_EN signal and powers up SoC supply rails.
- Device boots-up as defined in steps 3 to 5. DM SBL pills CAN_ONLY_IO status MMR to determine if the IORET mode was enabled. In addition, it can also compare the CAN ONLY IO WORD LATCHED to expected value to confirm the validity of CAN IO Voltages while the device was in IORET mode.
- DM reads the WKUP PADCFG bits to determine which pin caused the wake-up event
- DM writes in the Magic Word to disable IORET mode. DM then removes the ISO mode on the IOs, so they can go into normal mode of operation. This clears the IO buffer latches to reset state
- Device enters steady state operation
Note: Low Power Mode sequencing is controlled via Device Manager. For more information how to use Device Manager, see
TISCI API available at ti.com.