SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register has no storage. Read from this register returns 0.
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| Instance Name | Physical Address |
|---|---|
| MAIN_PSC0 | 0040 0018h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | GOSET | EPCSET | ERRSET | RESERVED | |||
| NONE | W | W | W | NONE | |||
| 0h | 0h | 0h | 0h | 0h | |||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | EPCEV | ERREV | ALLEV | ||||
| NONE | W | W | W | ||||
| 0h | 0h | 0h | 0h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:20 | RESERVED | NONE | 0h | Reserved |
| 19 | GOSET | W | 0h | GOSTAT Interrupt Set Reset Source: chip_rst.chip_1_rst_n |
| 18 | EPCSET | W | 0h | External Power Control Interrupt Set Reset Source: chip_rst.chip_1_rst_n |
| 17 | ERRSET | W | 0h | Combined Interrupt Set Reset Source: chip_rst.chip_1_rst_n |
| 16:3 | RESERVED | NONE | 0h | Reserved |
| 2 | EPCEV | W | 0h | External Power Control Interrupt Set Reset Source: chip_rst.chip_1_rst_n |
| 1 | ERREV | W | 0h | Re_evaluate Error Interrupt Reset Source: chip_rst.chip_1_rst_n |
| 0 | ALLEV | W | 0h | Re_evaluate combined PSC interrupt 0 Write of 0 has no effect
1 Re-evaluate the combined PSC interrupt
PSC_ALLINT |