SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Ethernet RGMII Boot Configuration Fields shows configuration pins assignment to functions when boot mode is the Ethernet RGMII mode.
| Field | Value | Description |
|---|---|---|
| Link Stat | 0 | Phy scan used for speed and duplex set up |
| 1 | RHMII status register used for speed and duplex set up |
Ethernet RMII Boot Configuration Fields shows configuration pins assignment to functions when boot mode is the Ethernet RMII mode.
| Field | Value | Description |
|---|---|---|
| Clkout | 0 | 50 MHz clock not generated on CLKOUT0 |
| 1 | 50 MHz clock generated on CLKOUT0 | |
| Clk src | 0 | External clock source for RMII1_REF_CLK |
| 1 | Internal clock source for RMII1_REF_CLK |
Table 5-18 shows configuration pins assignment to functions when the backup boot mode Ethernet. The Interface configuration field chooses which interface will be used (RGMII or RMII)
| Field | Value | Description |
|---|---|---|
| Interface | 0 | RGMII with internal TX delay |
| 1 | RMII with external clock source |
Table 5-19 summarizes the RGMII pin configuration done by ROM code for Ethernet boot device on RGMII port.
| Device Pin | Module Signal | Pull Enable | Pull Direction | Driver Index | Rx En/Dis | Pinmux Sel | Pad Configuration Register |
|---|---|---|---|---|---|---|---|
| RGMII1_TX_CTL | RGMII1_TX_CTL | Disable | NA | 0 | Disable | 0 | PADCONFIG75 |
| RGMII1_TXC | RGMII1_TXC | Disable | NA | 0 | Disable | 0 | PADCONFIG76 |
| RGMII1_TD0 | RGMII1_TD0 | Disable | NA | 0 | Disable | 0 | PADCONFIG77 |
| RGMII1_TD1 | RGMII1_TD1 | Disable | NA | 0 | Disable | 0 | PADCONFIG78 |
| RGMII1_TD2 | RGMII1_TD2 | Disable | NA | 0 | Disable | 0 | PADCONFIG79 |
| RGMII1_TD3 | RGMII1_TD3 | Disable | NA | 0 | Disable | 0 | PADCONFIG80 |
| RGMII1_RX_CTL | RGMII1_RX_CTL | Disable | NA | 0 | Enable | 0 | PADCONFIG81 |
| RGMII1_RXC | RGMII1_RXC | Disable | NA | 0 | Enable | 0 | PADCONFIG82 |
| RGMII1_RD0 | RGMII1_RD0 | Disable | NA | 0 | Enable | 0 | PADCONFIG83 |
| RGMII1_RD1 | RGMII1_RD1 | Disable | NA | 0 | Enable | 0 | PADCONFIG84 |
| RGMII1_RD2 | RGMII1_RD2 | Disable | NA | 0 | Enable | 0 | PADCONFIG85 |
| RGMII1_RD3 | RGMII1_RD3 | Disable | NA | 0 | Enable | 0 | PADCONFIG86 |
| MDIO0_MDIO | MDIO0_MDIO | Disable | NA | 0 | Enable | 0 | PADCONFIG87 |
| MDIO0_MDC | MDIO0_MDC | Disable | NA | 0 | Disable | 0 | PADCONFIG88 |
Table 5-20 summarizes the RMII pin configuration done by ROM code for Ethernet boot device on RMII port.
| Device Pin | Module Signal | Pull Enable | Pull Direction | Driver Index | Rx En/Dis | Pinmux Sel | Pad Configuration Register |
|---|---|---|---|---|---|---|---|
| RGMII1_RX_CTL | RMII1_RX_ER | Disable | NA | 0 | Enable | 1 | PADCONFIG81 |
| RGMII1_RXC | RMII1_REF_CLK | Disable | NA | 0 | Enable | 1 | PADCONFIG82 |
| RGMII1_RD0 | RMII1_RXD0 | Disable | NA | 0 | Enable | 1 | PADCONFIG83 |
| RGMII1_RD1 | RMII1_RXD1 | Disable | NA | 0 | Enable | 1 | PADCONFIG84 |
| RGMII1_TD0 | RMII1_TXD0 | Disable | NA | 0 | Disable | 1 | PADCONFIG77 |
| RGMII1_TD1 | RMII1_TXD1 | Disable | NA | 0 | Disable | 1 | PADCONFIG78 |
| RGMII1_TX_CTL | RMII1_TX_EN | Disable | NA | 0 | Disable | 1 | PADCONFIG75 |
| RGMII1_TXC | RMII1_CRS_DV | Disable | NA | 0 | Enable | 1 | PADCONFIG76 |
| RGMII1_TD3(1) | CLKOUT0 | Disable | NA | 0 | Enable | 1 | PADCONFIG80 |
| MDIO0_MDIO | MDIO0_MDIO | Disable | NA | 0 | Enable | 1 | PADCONFIG87 |
| MDIO0_MDC | MDIO0_MDC | Disable | NA | 0 | Disable | 1 | PADCONFIG88 |