SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Power management is accomplished using a standard clock stop protocol interface. When ASRC module is instructed to disable clocks for the internal clock domain, the internal clock network is shut down. This applies to the ASRC_SYS_CLK and ASRC_VBUS_CLK
Before a clock stop request is asserted at ASRC input, SW needs to confirm that ASRC is fully idle. HW will not check internal states to verify ASRC is idle. HW does check that no VBUSP transactions are ongoing before acknowledging the clock stop request.