Phase-Locked Loop circuits (PLLs) in the device are clock generator PLLs, which multiply the lower-frequency reference clock up to the operating frequency of the respective subsystem(s).
WARNING: PLL register descriptions are provided for
debug purposes only. These registers should not be manipulated directly from software. PLL
programming and configuration should only be performed using the appropriate APIs provided
by TISCI services in TI's Processor Software Development Kits (SDKs).
TISCI: Power Management (PM)