SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The IRQ_ENABLE_CLR register allows the interrupt sources to be manually disabled when writing a 1 to a specific bit. This register corresponds to fsas_fota_stat_err_pend/fsas_fota_stat_err_req interrupt output. Write 0: No action Write 1: Disable event Read 0: Event is disabled Read 1: Event is enabled
Return to Summary Table
| Instance Name | Physical Address |
|---|---|
| FSS0 | 0FC6 0050h + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | MCU_ERR | DAT_WRITE_ERR | DAT_READ_ERR | CFG_WRITE_ERR | CFG_READ_ERR | RESERVED | |
| NONE | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | NONE | |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:7 | RESERVED | NONE | 0h | Reserved |
| 6 | MCU_ERR | R/W1TC | 0h | MCU error enable clear Reset Source: vbus_mod_g_rst_n |
| 5 | DAT_WRITE_ERR | R/W1TC | 0h | Data interface write status error enable clear Reset Source: vbus_mod_g_rst_n |
| 4 | DAT_READ_ERR | R/W1TC | 0h | Data interface read status error enable clear Reset Source: vbus_mod_g_rst_n |
| 3 | CFG_WRITE_ERR | R/W1TC | 0h | Config interface write status error enable clear Reset Source: vbus_mod_g_rst_n |
| 2 | CFG_READ_ERR | R/W1TC | 0h | Config interface read status error enable clear Reset Source: vbus_mod_g_rst_n |
| 1:0 | RESERVED | NONE | 0h | Reserved |