SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
There are two SRAMs (each with size 4 KB - 512 words × 64-bit) in each MMCSD Subsystem. One SRAM dedicated for transmit and one SRAM dedicated for receive operations.
Figure 12-145 shows the ECC Aggregator block diagram.
Figure 12-210 ECC Aggregator Block DiagramFor more information about ECC Aggregator Registers, refer to MMCSD Registers.