SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Each channel has a dedicated input FIFO that is filled when an VBUS write (by a processor, EDMA, or DMA) occurs to that particular channel data register. The ASRC keeps tracks of the number of writes to the input FIFO and the number of reads that are sent into the processing path. The infifo interrupt will fire whenever the Input FIFO for the channel is below the threshold set in the ASRC_SRCFFCTRL_0[7:0] INFIFO_THRESHOLD register field. The interrupt will not be active until channel is enabled. Status for each FIFO can be checked in the ASRC_IFIRQENSTS status register. Once an INFIFO interrupt is fired, next interrupt will be generated only after INFIFO_THRESHOLD number of Audio RX Sync pulses has occured for that particular channel.
When the CPU is used to transfer data to ASRC, whenever an infifo_intr is triggered, SW needs to read the ASRC_IFIRQENSTS status register in order to determine which channels need to be serviced. Based on interrupt status register, software can trigger DMA to initiate transactions to channels. Data transfer will be in the same manner as described in ASRC Stream Mode Audio Data Write for Channel N with DMA triggered by software instead of infifo_evt event. After servicing the channel, SW needs to clear the interrupt for that particular channel.