SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Set Rising Edge Detection Register
Return to Summary Table
| Instance Name | Physical Address |
|---|---|
| GPIO0 | 0060 0074h |
| GPIO1 | 0060 1074h |
| MCU_GPIO0 | 0420 1074h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| SETRIS5 | |||||||
| R/W1TS | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| SETRIS5 | |||||||
| R/W1TS | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| SETRIS4 | |||||||
| R/W1TS | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SETRIS4 | |||||||
| R/W1TS | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:16 | SETRIS5 | R/W1TS | 0h | Writing 1 enables rising edge detection for GPIO bank 5 bits. Reset Source: mod_g_srst_n |
| 15:0 | SETRIS4 | R/W1TS | 0h | Writing 1 enables rising edge detection for GPIO bank 4 bits. Reset Source: mod_g_srst_n |