Packets received on the CPPI host port have a received packet priority (0 to 7 with 7 being the highest priority).
The received packet priority is determined as follows:
- If the first packet LTYPE = VLAN_LTYPE_SEL then the received packet priority is the packet priority (VLAN tagged and priority tagged packets).
- Else if the first packet LTYPE = 0x0800 and byte
14 (following the LTYPE) is equal to 0x4X, and DSCP_IPV4_EN is set in
CPSW3_CPSW_NU_CPSW_NU_CPPI_P0_CONTROL_REG or
CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_i_PN_CONTROL_REG register, then the received
packet priority is the 6-bit TOS field in byte 15 (upper 6 bits) mapped through
the port’s DSCP priority mapping registers (IPv4 packet).
- Else if the first packet LTYPE = 0x86DD and the
most significant nibble of byte 14 (following the LTYPE) is equal to 0x6, and
DSCP_IPV6_EN is set in CPSW3_CPSW_NU_CPSW_NU_CPPI_P0_CONTROL_REG or
CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_i_PN_CONTROL_REG register, then the received
packet priority is the 6-bit priority (in the 6-bits following the upper nibble
0x6) mapped through the port’s DSCP priority mapping registers (IPv6
packet).
- Else the received packet priority is the source (ingress) port priority
The CPPI Port (port 0) also has a received packet thread. The received packet thread is determined exactly as the received packet priority except for untagged packets. For untagged packets, the received packet thread is the packet streaming interface thread that the packet was received on (instead of the port VLAN priority or DSCP priority). The received packet thread is the hardware switch priority. The received packet thread only determines which hardware switch priority the packet should be sent to, the egress VLAN rules are identical to packets that were received on Ethernet ports (as determined by the header packet priority).
For CPPI ingress packets, the destination port
hardware switch priority is the below selected value remapped through
CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_i_PN_RX_PRI_MAP_REG:
- If the ingress packet is priority tagged or vlan tagged:
- If RX_REMAP_VLAN in
CPSW3_CPSW_NU_CPSW_NU_CPPI_P0_CONTROL_REG register is clear then the
destination hardware switch priority is the CPPI receive thread
number.
- If RX_REMAP_VLAN in
CPSW3_CPSW_NU_CPSW_NU_CPPI_P0_CONTROL_REG register is set then the the
destination hardware switch priority is the packet priority value. Port
transmit remapping (CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_i_PN_TX_PRI_MAP_REG
should remain the default value) is not compatible with this bit being
set, but remapping can be configured on port 0 receive.
- Else if the ingress packet has the first packet
LTYPE = 0x0800 and byte 14 (following the LTYPE) is equal to 0x4X, and
DSCP_IPV4_EN is set in CPSW3_CPSW_NU_CPSW_NU_CPPI_P0_CONTROL_REG register:
- If RX_REMAP_DSCP_V4 bit
in CPSW3_CPSW_NU_CPSW_NU_CPPI_P0_CONTROL_REG register is clear then the
destination hardware switch priority is the CPPI receive thread
number.
- If RX_REMAP_DSCP_V4 bit
in CPSW3_CPSW_NU_CPSW_NU_CPPI_P0_CONTROL_REG register is set then the
destination hardware switch priority is the 6-bit TOS field in byte 15
(upper 6-bits) mapped through the port’s DSCP priority mapping registers
(IPV4 packet). Port 1 transmit remapping
(CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_i_PN_TX_PRI_MAP_REG should remain the
default value) is not compatible with this bit being set, but remapping
can be configured on port 0 receive.
- Else if the ingress packet has the first packet LTYPE = 0x86DD and the most significant nibble of byte 14 (following the LTYPE) is equal to 0x6, and DSCP_IPV6_EN is set in P0_CONTROL_REG register:
- If RX_REMAP_DSCP_V6 bit in
CPSW3_CPSW_NU_CPSW_NU_CPPI_P0_CONTROL_REG register is clear then the
destination hardware switch priority is the CPPI receive thread
number.
- If RX_REMAP_DSCP_V6 bit in
CPSW3_CPSW_NU_CPSW_NU_CPPI_P0_CONTROL_REG register is set then the
destination hardware switch priority is the 6-bit priority (in the
6-bits following the upper nibble 0x6) mapped through the port’s DSCP
priority mapping registers (IPV6 packet). Port 1 transmit remapping
(CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_i_PN_TX_PRI_MAP_REG should remain the
default value) is not compatible with this bit being set, but remapping
can be configured on port 0 receive.
- Else the ingress packet is non-tagged and the destination hardware switch priority is the CPPI receive thread number.