SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The Kick1 register allows writing to unlock the kick1 data and the kicker mechanism to write to other MMRs. The written data must be 0x95a4f1e0 to unlock this register. If this is unlocked after the kick0 register is unlocked then the kicker mechanism is unlocked
The HOST must ensure that there is at least 60 microseconds of delay between a "new" lock state to a "new" unlock state. This should be implemented by ensuring that RTC_SYNCPEND.WR_PEND is 0 before performing the unlock writes. This is a consequence of the limitation that the functional unlock sequence must not be written while the mechanism is unlocked; if the unlock sequence is written at the wrong time, then the core domain and battery domain will not agree about their unlocked status. This will not be diagnosable in software and there is no recommended error recovery sequence for this condition.
For No Analog support, leave it unlocked.
Return to Summary Table
| Instance Name | Physical Address |
|---|---|
| WKUP_RTCSS0 | 2B1F 0074h + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| KICK1 | |||||||
| W | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| KICK1 | |||||||
| W | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| KICK1 | |||||||
| W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| KICK1 | |||||||
| W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:0 | KICK1 | W | 0h | Kick1 MMR, must write 0x95a4f1e0 to unlock this register and the other MMRs |