SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Specifies the status of the DCC Module.
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| Instance Name | Physical Address |
|---|---|
| DCC0 | 0080 0014h |
| DCC1 | 0080 4014h |
| DCC2 | 0080 8014h |
| DCC3 | 0080 C014h |
| DCC4 | 0081 0014h |
| DCC5 | 0081 4014h |
| DCC6 | 0081 8014h |
| DCC7 | 0081 C014h |
| DCC8 | 0082 0014h |
| MCU_DCC0 | 04C0 0014h |
| MCU_DCC1 | 04C1 0014h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | DONEFLG | ERRFLG | |||||
| NONE | R/W1TC | R/W1TC | |||||
| 0h | 0h | 0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:2 | RESERVED | NONE | 0h | Reserved |
| 1 | DONEFLG | R/W1TC | 0h | Indicates when single-shot mode is complete without error. Writing a 1 to this bit clears the flag. User, privilege, and debug mode (read): 0 = single-shot mode is not done 1 = single-shot mode is done Privilege and debug mode (write): 0 = no effect 1 = clear the done flag |
| 0 | ERRFLG | R/W1TC | 0h | Indicates whether or not an error has occured. Writing a 1 to this bit clears the flag. User, privilege, and debug mode (read): 0 = an error has not occurred 1 = an error has occurred Privilege and debug mode (write): 0 = no effect 1 = clear the error flag |