SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Wrapper register containing static settings. All bits in this register directly drive the USB2 PHY inputs. Please refer to USB2 PHY user guide for more information.
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| Instance Name | Physical Address |
|---|---|
| USB0 | 0F90 0008h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED31_9 | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED31_9 | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED31_9 | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED31_9 | RESERVED4_3 | VBUS_SEL | LANE_REVERSE | ||||
| R | R/W | R/W | R/W | ||||
| 0h | 0h | 1h | 0h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:5 | RESERVED31_9 | R | 0h | Reserved bits |
| 4:3 | RESERVED4_3 | R/W | 0h | Reserved bits |
| 2:1 | VBUS_SEL | R/W | 1h | This register directly drives the vbus_sel[1:0] input to the PHY. VBUS select - 00: VBUS = 5.25V/3.3V, 01: VBUS/3 external divider is active, so VBUS could be upto 11V. Reset Source: cfg_srst_n |
| 0 | LANE_REVERSE | R/W | 0h | This register directly drives the lane_reverse input to USB2 PHY. Lane reverse selection. When set, this bit indicates that D+ and D- lines have to be swapped. Reset Source: cfg_srst_n |