SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register contains the bits to indicate flush in STPMI2ATB. It also controls priority control for other conditions in STPMI2ATB.
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| Instance Name | Physical Address |
|---|---|
| C7X256V1_DEBUG | 0007 3804 0114h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RSVD1 | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RSVD1 | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RSVD1 | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RSVD1 | FORCE_FLUSH | RSVD0 | ASYNC_PE | AUTO_FLUSH | |||
| R | R/W | R | R/W | R/W | |||
| 0h | 0h | 7h | 0h | 0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:6 | RSVD1 | R | 0h | reserved |
| 5 | FORCE_FLUSH | R/W | 0h | Forces a flush operation: 1 indicates force a flush, automatically clears after the operation is complete. Refer to 2.10. A '0' is not a valid value to be written at any point of time. It will be ignored. This flush will happen only after any current flush on ATB boundary is completed. |
| 4:2 | RSVD0 | R | 7h | reserved |
| 1 | ASYNC_PE | R/W | 0h | ASYNC Sequence Priority Enable: 0 indicates ASYNC packet priority is lower than normal trace. 1 indicates priority escalates on second synchronization request |
| 0 | AUTO_FLUSH | R/W | 0h | Enable ATB Auto-flush: 0 indicates auto flush disabled. 1 indicates auto flush enabled. On every complete data (ATDATA:WIDTH) in the fifo written, data is exported out when ATREADY is asserted. This needs to be written only once before client IP enabled. |