SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Controls various parameters of the cotroller state.
Return to Summary Table
| Instance Name | Physical Address |
|---|---|
| FSS1 | 0FC8 0004h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | OSPI_32B_DISABLE_MODE | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DISXIP | OSPI_DDR_DISABLE_MODE | RESERVED | ECC_DISABLE_ADR | FSS_AES_EN_IPCFG | HB_OSPI | ECC_EN | |
| R/W | R/W | NONE | R/W | R | R/W | R/W | |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:9 | RESERVED | NONE | 0h | Reserved |
| 8 | OSPI_32B_DISABLE_MODE | R/W | 0h | 0 OSPI 32bit mode enabled. 1 OSPI 32bit mode disabled Reset Source: vbus_mod_g_rst_n |
| 7 | DISXIP | R/W | 0h | 0 XIP Prefetch Enabled. 1 XIP prefetch disabled Reset Source: vbus_mod_g_rst_n |
| 6 | OSPI_DDR_DISABLE_MODE | R/W | 0h | 0 OSPI DDR mode enabled. 1 OSPI DDR mode disabled Reset Source: vbus_mod_g_rst_n |
| 5:4 | RESERVED | NONE | 0h | Reserved |
| 3 | ECC_DISABLE_ADR | R/W | 0h | 0 Block address within ECC calculation, 1 Block address not within ECC calculation Reset Source: vbus_mod_g_rst_n |
| 2 | FSS_AES_EN_IPCFG | R | 0h | 1 select security, 0 disable security Reset Source: vbus_mod_g_rst_n |
| 1 | HB_OSPI | R/W | 0h | 1 select hb path. 0 select ospi path Reset Source: vbus_mod_g_rst_n |
| 0 | ECC_EN | R/W | 0h | 0 ECC disabled. 1 ECC enabled Reset Source: vbus_mod_g_rst_n |