SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The receive bit stream format register (RFMT) configures the receive data format.
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| Instance Name | Physical Address |
|---|---|
| MCASP0 | 02B0 0068h |
| MCASP1 | 02B1 0068h |
| MCASP2 | 02B2 0068h |
| MCASP3 | 02B3 0068h |
| MCASP4 | 02B4 0068h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED80 | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED80 | RDATDLY | ||||||
| R | R/W | ||||||
| 0h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RRVRS | RPAD | RPBIT | |||||
| R/W | R/W | R/W | |||||
| 0h | 0h | 0h | |||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RSSZ | RBUSEL | RROT | |||||
| R/W | R/W | R/W | |||||
| 0h | 0h | 0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:18 | RESERVED80 | R | 0h | |
| 17:16 | RDATDLY | R/W | 0h | Receive bit delay. 0 0-bit delay. The first receive data bit,
AXRn, occurs in same ACLKR cycle as the
receive frame sync (AFSR).
1 1-bit delay. The first receive data bit,
AXRn, occurs one ACLKR cycle after the
receive frame sync (AFSR).
2 2-bit delay. The first receive data bit,
AXRn, occurs two ACLKR cycles after the
receive frame sync (AFSR).
3 Reserved. |
| 15 | RRVRS | R/W | 0h | Receive serial bitstream order. 0 Bitstream is LSB first. No bit reversal is
performed in receive format bit reverse
unit.
1 Bitstream is MSB first. Bit reversal is
performed in receive format bit reverse
unit. |
| 14:13 | RPAD | R/W | 0h | Pad value for extra bits in slot not belonging to the word. This field only applies to bits when RMASK[n] = 0. 0 Pad extra bits with 0.
1 Pad extra bits with 1.
2 Pad extra bits with one of the bits from
the word as specified by RPBIT bits.
3 Reserved. |
| 12:8 | RPBIT | R/W | 0h | RPBIT value determines which bit [as read by the CPU or DMA from RBUF[n]] is used to pad the extra bits. This field only applies when RPAD = 2h. 0 Pad with bit 0 value.
1 Pad with bit 1 to bit 31 value from 1h to
1Fh. |
| 7:4 | RSSZ | R/W | 0h | Receive slot size. 0 Reserved. 1 Reserved. 2 Reserved. 3 Slot size is 8 bits. 4 Reserved 5 Slot size is 12 bits. 6 Reserved 7 Slot size is 16 bits. 8 Reserved 9 Slot size is 20 bits. 10 Reserved 11 Slot size is 24 bits 12 Reserved 13 Slot size is 28 bits. 14 Reserved 15 Slot size is 32 bits. |
| 3 | RBUSEL | R/W | 0h | Selects whether reads from serializer buffer XRBUF[n] originate from the configuration bus [CFG] or the data [DAT] port. 0 Reads from XRBUF[n] originate on data port.
Reads from XRBUF[n] on configuration bus
are ignored.
1 Reads from XRBUF[n] originate on
configuration bus. Reads from XRBUF[n] on
data port are ignored. |
| 2:0 | RROT | R/W | 0h | Right-rotation value for receive rotate right format unit. 0 Rotate right by 0 (no rotation). 1 Rotate right by 4 bit positions. 2 Rotate right by 8 bit positions. 3 Rotate right by 12 bit positions. 4 Rotate right by 16 bit positions. 5 Rotate right by 20 bit positions. 6 Rotate right by 24 bit positions. 7 Rotate right by 28 bit positions. |