This device includes advanced power, reset, and clock management debug capabilities, including:
- Wakeup support for debug logic: logic within the device is able to sense JTAG activity and ensure that debug logic is on and able to service JTAG requests.
- Reset isolation: critical configuration and trace data paths and logic are not sensitive to warm reset
- Configuration independence: debug configuration occurs over a debug-only interconnect, separate from SoC traffic to ensure debug logic remains available even during deadlock scenarios.
- Power-AP: a CoreSight compliant Access Port (AP) developed by TI that provides a standard interface for debug tooling to access status and control over power, reset, and clocking for the system and various LPSC-defined sub-domains.