SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Debug trace control register
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| Instance Name | Physical Address |
|---|---|
| USB0 | 0070 3080h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RSVD | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RSVD | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RSVD | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RSVD | EN_OUT_EP14 | EN_OUT_EP15 | EN_IN_EP14 | EN_IN_EP15 | |||
| R | R/W | R/W | R/W | R/W | |||
| 0h | 0h | 0h | 0h | 0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:4 | RSVD | R | 0h | Reserved bits Reset Source: cfg_srst_n |
| 3 | EN_OUT_EP14 | R/W | 0h | Debug trace enable for OUT Endpoint 14 Reset Source: cfg_srst_n |
| 2 | EN_OUT_EP15 | R/W | 0h | Debug trace enable for OUT Endpoint 15 Reset Source: cfg_srst_n |
| 1 | EN_IN_EP14 | R/W | 0h | Debug trace enable for IN Endpoint 14 Reset Source: cfg_srst_n |
| 0 | EN_IN_EP15 | R/W | 0h | Debug trace enable for IN Endpoint 15 Reset Source: cfg_srst_n |