SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The Map Register defines the fields for the initiator Iam275_c7xv_wrap_0_main_0.c7xv_soc per channel.
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| Instance Name | Physical Address |
|---|---|
| CBASS_MEM0 | 45D3 0100h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ORDERID | RESERVED | ||||||
| R/W | NONE | ||||||
| 0h | 0h | 0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:8 | RESERVED | NONE | 0h | Reserved |
| 7:4 | ORDERID | R/W | 0h | orderid signal for channel N. Selects to route for load balancing (0-7 uses one route, 8-15 another). Also used by DDR4/LPDDR4 re-ordering to maximize throughput. Order of transactions is only guaranteed with the same orderid Reset Source: domain_default_rst_mod_g_rst_n |
| 3 | RESERVED | NONE | 0h | Reserved |