SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
There is a register used for controlling the priority of the MLBSS on the system interconnect. This is done through the MLBSS_DMA_CTRLMLBSS_DMA_CTRL[2-0] PRIORITY bit field. Setting this bit field to 0h means that the MLBSS traffic has highest priority over the other initiator traffics. A value of 7h is for lowest priority.